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參數(shù)資料
| 型號(hào)： | UPD2845GR-E2 |
| 廠商： | NEC Corp. |
| 英文描述： | 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM |
| 中文描述： | 1伏，1.3毫安，94MHz PLL頻率合成器大規(guī)模集成電路的尋呼系統(tǒng) |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 144K |
| 代理商： | UPD2845GR-E2 |
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3
P
PD2845GR
PIN EXPLANATION
PIN No.
PIN NAME
I/O
EXPLANATION FOR FUNCTION
1
V
DD1
Supply voltage to PLL block
2
F
IN
I
Frequency Input
3
GND
Ground
4
FR
O
Test pin for monitor.
Normally used as PLL, output L should be selected by test bit and this pin should be
opened. (Refer to setting for reference counter on 11 page)
5
RESET
I
Test pin for monitor reset. (Refer to RESET on 12 page)
Normally used as PLL, this pin should be grounded.
6
EO
O
Internal charge pump output. In the case of passive filter, this output should be used.
Input signal phase f
p
vs. reference signal f
r
f
p
> f
r
: Low output
f
p
< f
r
: High output
f
p
= f
r
: High-impedance
7
8
EOP
EON
O
O
Outputs for external charge pump. In the case of active filter, this outputs should be used.
EOP : PCH open drain
EON : NCH open drain
9
V
DD2
Supply voltage to charge pump.
10
NC
Non Connection.
11
PS
I
Control bias input for power-save (Refer to Power-save on 12 page).
12
DATA
I
Data input for divided ratio.
13
CLK
I
Clock input for shift register.
14
LE
I
Latch enable input.
15
16
XO
XI
O
I
X’tal oscillator connection pin.
EOP
EON
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