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參數(shù)資料
| 型號(hào)： | UPD2845GR-E2 |
| 廠商： | NEC Corp. |
| 英文描述： | 1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI FOR PAGER SYSTEM |
| 中文描述： | 1伏，1.3毫安，94MHz PLL頻率合成器大規(guī)模集成電路的尋呼系統(tǒng) |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 144K |
| 代理商： | UPD2845GR-E2 |
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12
P
PD2845GR
Power-save and RESET
Power-save (PIN 11)
Power-save-mode can be selected by input data to PS pin.
H; operation mode
L; power-save-mode
On the power-save-mode, reference oscillator and prescaler turn off and error-outs (EO, EOP, EON) output Hi-
impedance but shift register data is remained. Serial data can be received in power-save-mode.
Note:
Power-save usage for initial V
CC
supplying
To prevent unstable mode at initial V
CC
supplying, Power-save-mode must be selected. After counter data
setting, normal operation mode can be selected.
RESET (PIN 5)
Reset-mode can be selected by input data to RESET pin.
H; reset-mode
L(GND or Open); Normal operation.
On the reset-mode, reference oscillator/prescalers turn off and error-outs (EO, EOP, EON) output Hi-impedance.
Shift-register data is initialized.
This reset-mode should be used at LSI testing, normally use as PLL, RESET pin should be opened or grounded.
Supplementary explanation:
When RESET pin bias is switched from H to L, initial divide ratios can be set automatically as follows
Input signal divider: NT = 10372
13 bit programmable reference counter: R = 1 280 (RT = 2 560)
These divide ratios make PLL loop without controller on condition as follows
f
in
= 51.86 MHz
f
x’tal
= 12.8 MHz
f
p
= f
r
= 5.0 kHz
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