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參數資料
| 型號： | UPD17242UC-XXX-5A4 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.5 MHz, MICROCONTROLLER, PDSO30 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-30 |
| 文件頁數： | 37/102頁 |
| 文件大?。?/td> | 953K |
| 代理商： | UPD17242UC-XXX-5A4 |
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4
Data Sheet U15002EJ1V1DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
DIFFERENCES BETWEEN
PD17246 SUBSERIES, PD17236 SUBSERIES, AND PD17255
SUBSERIES (2/2)
Item
PD17246 Subseries
PD17236 Subseries
PD17225 Subseries
STOP mode release
<1> When any of pins P0A0
When any of pins P0A0 to
condition
to P0A3 goes low
P0A3 and P0B0 to P0B3 goes
<2> When pins P0B0 to P0B3,
<2> When pins P0B0 to P0B3, low
P0C0 to P0C3, and P0D0
to P0D3 are used as input
to P0D3 are used as
pins and when any of
input pins and when any
them goes low
of them goes low
<3> When an interrupt
request (IRQ) of the
interrupt for which the IP
flag is set is generated at
flag is set is generated
the rising edge or falling
at the rising edge or
edge of the INT pin
falling edge of the INT
<4> When P0E0 to P0E3 are
pin
used as input pins when
a key matrix is used and
when any of these pins
goes low
<5> When P1A0 to P1A2 and
P1B0 are used as input
pins when a key matrix is
used and when the level
of any of these pins
equals the set clear level
Carrier frequency
Selected by register file
Selected by mask option
7.8 kHz to 1 MHz
(fX = 4 MHz)
(after reset: fX/2)
<1> If carrier generation
<1> If carrier generation clock
clock is fX/2: 7.8 kHz to
is fX/2: 3.9 kHz to 1 MHz
1 MHz
<2> If carrier generation clock
<2> If carrier generation
is fX: 7.8 kHz to 2 MHz
clock is fX: 15.6 kHz to
<3> If carrier generation clock
2 MHz
is 2fX: 15.6 kHz to 4 MHz
NRZ low-level period
NRZLTMM: 8 bits
NRZLTMM: 7 bits (bit 7 is REM output control bit)
setting modulo register
(REM output control bit is bit
NRZHTMM: 7 bits (bit 7 is fixed to 0)
(NRZLTMM) and NRZ
1 of register file at address
high-level period setting
12H)
modulo register
NRZHTMM: 8 bits
(NRZHTMM)
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