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參數(shù)資料
| 型號： | UPD17240MC-XXX-5A4-A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO30 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-30 |
| 文件頁數(shù)： | 62/102頁 |
| 文件大?。?/td> | 668K |
| 代理商： | UPD17240MC-XXX-5A4-A |
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62
Data Sheet U15002EJ1V0DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
8.
INTERRUPT FUNCTIONS
8.1
Interrupt Sources
PD17246 is provided with three interrupt sources.
When an interrupt has been acknowledged, the program execution automatically branches to a predetermined
address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table
8-1.
Table 8-1. Vector Address
Priority
Interrupt Source
Ext/Int
Vector Address
1
8-bit timer
Internal
0004H
2
INT pin rising and falling edges
External
0003H
3
Basic interval timer
Internal
0002H
Remark
0001H is normal address
When more than one interrupt request is issued at the same time, the interrupts are acknowledged in sequence,
starting from the one with the highest priority.
Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which
an interrupt is acknowledged is that the interrupt is enabled by the EI instruction. While the DI instruction is executed,
or while an interrupt is acknowledged, the interrupt is disabled.
To enable acknowledgement of an interrupt after the interrupt has been processed, the EI instruction must be
executed before the RETI instruction. Acknowledging the interrupt is enabled by the EI instruction after the instruction
next to the EI instruction has been executed. Therefore, no interrupt can be acknowledged between the EI and RETI
instructions.
Caution In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack
by the hardware, to a maximum of three levels. Also, within the interrupt processing contents,
when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents
are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt
processing, DBF and WR be saved by software to RAM, and immediately before finishing
interrupt processing, the saved contents be returned to their original location.
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