參數(shù)資料
型號(hào)： UPD17240MC-XXX-5A4-A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO30
封裝： 0.300 INCH, PLASTIC, SSOP-30
文件頁(yè)數(shù)： 18/102頁(yè)
文件大?。?/td> 668K
代理商： UPD17240MC-XXX-5A4-A
22
Data Sheet U15002EJ1V0DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.4
Data Memory (RAM)
The data memory (RAM) stores data for operations and control. It can always be read/written by instructions.
2.4.1
Memory configuration
Figure 2-6 shows the configuration of the data memory (RAM).
The data memory consists of four “banks”: BANK0, BANK1, BANK2, and BANK3.
In each bank, every 4 bits of data are assigned an address. The higher 3 bits of the address indicate a “row address”
and the lower 4 bits of the address indicate a “column address”. For example, a data memory location indicated by
row address 1H and column address 0AH is termed a data memory location at address 1AH. Each address stores
data of 4 bits (= 1 nibble).
In addition, the data memory is divided into the following six functional blocks.
(1) System register (SYSREG)
A system register (SYSREG) is resident on addresses 74H to 7FH (12 nibbles) of each bank. In other words,
each bank has the same system register at its addresses 74H to 7FH.
(2) Data buffer (DBF)
A data buffer is resident on addresses 0CH to 0FH (4 nibbles) of bank 0 of the data memory.
The reset value is 0320H.
(3) General register (GR)
A general register is resident on any row (16 nibbles) of any bank of the data memory.
The row address of the general register is pointed to by the general register pointer (RP) in the system register
(SYSREG).
(4) Port register
A port data register is resident on addresses 6FH, and 70H to 73H of BANK0 and addresses 70H and 71H
of BANK1 (7 nibbles) of the data memory.
No data can be written to or read from addresses 72H and 73H of BANK1 and addresses 70H to 73H of BANK2
or BANK3.
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