參數(shù)資料
型號： UPD17240MC-XXX-5A4-A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO30
封裝： 0.300 INCH, PLASTIC, SSOP-30
文件頁數(shù)： 31/102頁
文件大小： 668K
代理商： UPD17240MC-XXX-5A4-A
34
Data Sheet U15002EJ1V0DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
3.
PORTS
3.1
Port 0A (P0A0 to P0A3)
This is a 4-bit input port. Data is read using port register P0A (address 70H of BANK0). This port is a CMOS input
port with a pull-up resistor, and can be used as the key return input lines of a key matrix.
In the standby mode, the standby status is released when a low level is input to at least one of these pins.
3.2
Port 0B (P0B0 to P0B3)
This is a 4-bit I/O port which can be set to the input or output mode in 1-bit units by using P0BBIO (address 26H)
of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of
a key matrix.
The data input to this port can be read or the data output from this port can be set by using the P0B register (address
71H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 k
is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
After reset, this port is set to the input mode.
3.3
Port 0C (P0C0 to P0C3)
This is a 4-bit I/O port which can be set to the input or output mode in 4-bit units (group I/O) by using P0CDGIO
(bit 2 of address 37H) of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of
a key matrix.
The data input to this port can be read or the data output from this port can be set by using the P0C register (address
72H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 k
is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
After reset, this port is set to the output mode and outputs a low level.
3.4
Port 0D (P0D0 to P0D3)
This is a 4-bit I/O port which can be set to the input or output mode in 4-bit units (group I/O) by using P0CDGIO
(bit 3 of address 37H) of the register file.
In the input mode, each bit of this port serves as a CMOS input pin with a pull-up resistor and can be used as a
key return input line of a key matrix. In the standby mode, the standby status is released when a low level is input
to at least one of these pins.
In the output mode, these pins serve as N-ch open-drain output pins and can be used as the key source lines of
a key matrix.
The data input to this port can be read or the data output from this port can be set by using the P0D register (address
73H of BANK0). When this port is read in the output mode, the contents of the output latch are read.
In the input mode, a pull-up resistor of 200 k
is connected to each bit of this port. In the output mode, the pull-
up resistor is disconnected.
After reset, this port is set to the output mode and outputs a low level.
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