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參數(shù)資料
| 型號： | UD61466DC07 |
| 英文描述： | AC LINE SWITCH |
| 中文描述： | x4靜態(tài)列模式DRAM |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 175K |
| 代理商： | UD61466DC07 |
December 12, 1997
5
UD61464
Dynamic Characteristics
3)
Symbol
Min.
Max.
Unit
Alt.
IEC
DC07
DC08
DC07
DC08
p
ALL CYCLES
Transition Time (Rise and Fall)
4)
t
T
t
t
3
3
50
50
ns
RAS Precharge Time
CAS Precharge Time
t
RP
t
CP
t
w(RASH)
t
w(CASH)
50
10
60
10
ns
ns
Row Address Set-up Time
Column Address Set-up Time
t
ASR
t
ASC
t
su(RA-RAS)
t
su(CA-CAS)
0
0
0
0
ns
ns
Row Address Hold Time
Column Address Hold Time ref. to RAS
Column Address Hold Time
t
RAH
t
AR
t
CAH
t
h(RAS-RA)
t
h(RAS-CA)
t
h(CAS-CA)
10
55
15
10
60
15
ns
ns
ns
Output Buffer Turn-off Delay Time
Output Buffer Turn-off Delay Time from G
5)
5)
t
OFF
t
OEZ
t
v(CAS)
t
v(G)
0
0
0
0
20
20
20
20
ns
ns
CAS to RAS Precharge Time
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to Output in Low-Z
Refresh Period
6)
t
CRP
t
RAD
t
RAL
t
CLZ
t
REF
t
CASH-RASL
RAS-CA
t
CA-RASH
t
CASL-QX
rf
5
15
35
0
5
15
40
0
35
4
40
4
ns
ns
ns
ns
ms
p
READ
Random Read Cycle Time
7)
t
RC
t
cR
130
150
ns
Access Time from RAS
Access Time from Column Address
Access Time from CAS
G Access Time
8)
8)
8)
8)
t
RAC
t
AA
t
CAC
t
OEA
t
a(RAS)
t
a(CA)
t
a(CAS
)
t
a(G)
70
35
20
20
80
40
20
20
ns
ns
ns
ns
RAS Pulse Width
CAS Pulse Width
t
RAS
t
CAS
t
w(RASL)
t
w(CASL)
70
20
80
20
10000
10000
10000
10000
ns
ns
Read Command Set-up Time
t
RCS
t
su(R-CAS)
0
0
ns
Read Command Hold Time ref. to RAS
Read Command Hold Time
9)
9)
t
RRH
t
RCH
t
h(RAS-R)
t
h(CAS-R)
0
0
0
0
ns
ns
RAS to CAS Delay Time
CAS Hold Time
RAS Hold Time
RAS Hold Time referenced to G
6)
t
RCD
t
CSH
t
RSH
t
ROH
t
RASL-CASL
t
RASL-CASH
t
CASL-RASH
GL-RASH
20
70
20
10
20
80
20
10
50
60
ns
ns
ns
ns
Remarks: see page 7
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參數(shù)描述 |
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