參數(shù)資料
型號: TWR-MCF51JE
廠商: Freescale Semiconductor
文件頁數(shù): 28/47頁
文件大小: 0K
描述: TOWER SYSTEM BOARD MCF51JE
標準包裝: 1
系列: ColdFire®, Flexis™
類型: MCU
適用于相關(guān)產(chǎn)品: Freescale 電源塔系統(tǒng),MCF51JE
所含物品:
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor
34
3.12
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.12.1
Control Timing
Table 20. Control Timing
#
Parameter
Symbol
Minimum
Typica
l1
1
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated.
Maximum
Unit
C
1
Bus frequency (tcyc = 1/fBus)
VDD 1.8 V
fBus
dc
10
MHz
D
VDD > 2.1 V
fBus
dc
20
MHz
D
VDD > 2.4 V
fBus
dc
25.165
MHz
D
2
Internal low-power oscillator period
tLPO
700
1000
1300
s
P
3
External reset pulse width2
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset
requests from internal sources.
(tcyc =
1/fSelf_reset)
textrst
100
ns
D
4
Reset low drive
trstdrv
66 x tcyc
——
ns
D
5
Active background debug mode
latch setup time
tMSSU
500
ns
D
6
Active background debug mode
latch hold time
tMSH
100
ns
D
7
IRQ pulse width
Asynchronous path2
Synchronous path3
3
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be
recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL
100
1.5 x tcyc
——
ns
D
8
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 x tcyc
——
ns
D
9
Port rise and fall time (load = 50 pF)4, Low Drive
4
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 105 C.
Slew rate
control disabled
(PTxSE = 0)
tRise, tFall
—11
ns
D
Slew rate
control enabled
(PTxSE = 1)
tRise, tFall
—35
ns
D
Slew rate
control disabled
(PTxSE = 0)
tRise, tFall
—40
ns
D
Slew rate
control enabled
(PTxSE = 1)
tRise, tFall
—75
ns
D
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