參數(shù)資料
型號： TWR-MCF51JE
廠商： Freescale Semiconductor
文件頁數(shù)： 24/47頁
文件大?。?/td> 0K
描述： TOWER SYSTEM BOARD MCF51JE
標(biāo)準(zhǔn)包裝： 1
系列： ColdFire®, Flexis™
類型： MCU
適用于相關(guān)產(chǎn)品： Freescale 電源塔系統(tǒng)，MCF51JE
所含物品： 板
MCF51JE256 Datasheet, Rev. 4
Preliminary Electrical Characteristics
Freescale Semiconductor
30
5
Total deviation of trimmed DCO
output frequency over voltage and
temperature
over voltage and
temperature
f
dco_t
—
1.0
2
%fdco
P
over fixed voltage
and temp range
of 0 - 70
C
—
0.5
1
%fdco
C
6
Acquisition time
FLL2
tfll_acquire
——
1
ms
C
PLL3
tpll_acquire
——
1
ms
D
7
Long term Jitter of DCO output clock (averaged over 2mS
interval) 4
CJitter
—
0.02
0.2
%fdco
C
8
VCO operating frequency
fvco
7.0
—
55.0
MHz
D
9
PLL reference frequency range
fpll_ref
1.0
—
2.0
MHz
D
10
Jitter of PLL output clock measured
over 625 ns
Long term
fpll_jitter_625
ns
—
0.5664
—%fpll
D
11 Lock frequency tolerance
Entry5
Dlock
1.49
—
2.98
%
D
Exit6
Dunl
4.47
—
5.97
%
D
12 Lock time
FLL
tfll_lock
——
tfll_acquire+
1075(1/fint_t)
sD
PLL
tpll_lock
——
tpll_acquire+
1075(1/fpll_ref)
sD
13 Loss of external clock minimum frequency - RANGE = 0
floc_low
(3/5) x
fint_t
—
kHz
D
14 Loss of external clock minimum frequency - RANGE = 1
floc_high
(16/5) x
fint_t
——
kHz
D
1
This should not exceed the maximum CPU frequency of 50.33 MHz.
2
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is
changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is
being used as the reference, this specification assumes it is already running.
3
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI)
to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS. Measurements are
made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via
VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
5
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG is already
in lock, then the MCG may stay in lock.
6
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.
Table 17. MCG (Temperature Range = –40 to 105
C Ambient) (continued)
#
Rating
Symbol
Min
Typical
Max
Unit
C
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TWR-MCF51-JE-KIT 制造商:Freescale Semiconductor 功能描述:KIT DEV TOWER MCF51JE 制造商:Freescale Semiconductor 功能描述:TOWER SYS KIT, MCF51JE, TWR-SER/ELEV
TWR-MCF51JE-KIT 功能描述:開發(fā)板和工具包 - COLDFIRE KIT MCU Bd Fsl Tower RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Kits 工具用于評估:MCF53017 核心:ColdFire V3 接口類型:Ethernet, UART, USB 工作電源電壓:12 V
TWR-MCF51JF 功能描述:開發(fā)板和工具包 - COLDFIRE MCF51QM Tower Module RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Kits 工具用于評估:MCF53017 核心:ColdFire V3 接口類型:Ethernet, UART, USB 工作電源電壓:12 V
TWR-MCF51JF-KIT 功能描述:開發(fā)板和工具包 - COLDFIRE MCF51JF Tower Kit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Kits 工具用于評估:MCF53017 核心:ColdFire V3 接口類型:Ethernet, UART, USB 工作電源電壓:12 V
TWR-MCF51JG 制造商:Freescale Semiconductor 功能描述:TWR-MCF51JG - Boxed Product (Development Kits) 制造商:Freescale Semiconductor 功能描述:MOD TOWER SYSTEM MCF51JX
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