參數(shù)資料
型號： TVP5160PNP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： GREEN, PLASTIC, HTQFP-128
文件頁數(shù)： 97/111頁
文件大?。?/td> 1400K
代理商： TVP5160PNP
SLES135E
– FEBRUARY 2005 – REVISED APRIL 2011
Table 3-131. Interrupt Status 1
Subaddress
F3h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full: Masked status of FIFO
0 = FIFO not full
1 = FIFO was full during write to FIFO, see the interrupt mask 1 register at subaddress F5h
The masked or unmasked status is set in the interrupt mask 1 register.
Table 3-132. Interrupt Mask 0
Subaddress
F4h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed mask
0 = Disabled (default)
1 = Enabled FIFO_THRES interrupt
TTX: Teletext data available mask
0 = Disabled (default)
1 = Enabled TTX available interrupt
WSS/CGMS: WSS/CGMS data available mask
0 = Disabled (default)
1 = Enabled WSS/CGMS available interrupt
VPS/Gemstar: VPS/Gemstar data available mask:
0 = Disabled (default)
1 = Enabled VPS/Gemstar available interrupt
VITC: VITC data available mask:
0 = Disabled (default)
1 = Enabled VITC available interrupt
CC F2: CC field 2 data available mask
0 = Disabled (default)
1 = Enabled CC field 2 available interrupt
CC F1: CC field 1 data available mask
0 = Disabled (default)
1 = Enabled CC field 1 available interrupt
LINE: Line number interrupt mask
0 = Disabled (default)
1 = Enabled Line_INT interrupt
The host interrupt mask 0 and 1 registers can be used by the external processor to mask unnecessary interrupt sources for interrupt status
0 and 1 register bits, and for the external interrupt pin. The external interrupt is generated from all nonmasked interrupt flags.
Table 3-133. Interrupt Mask 1
Subaddress
F5h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full: FIFO full mask
0 = Disabled (default)
1 = Enabled FIFO full interrupt
86
Internal Control Registers
Copyright
2005–2011, Texas Instruments Incorporated
focus.ti.com: TVP5160
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