參數(shù)資料
型號： TVP5160PNP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： GREEN, PLASTIC, HTQFP-128
文件頁數(shù)： 19/111頁
文件大?。?/td> 1400K
代理商： TVP5160PNP
SLES135E
– FEBRUARY 2005 – REVISED APRIL 2011
Table 1-1. Terminal Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Analog Video
VI_1
3
I
VI_x: analog video inputs
VI_2
4
Up to 12 composite, 6 S-Video, or 3 component video inputs (or combinations thereof) can
VI_3
5
be
VI_4
7
supported. Also, 4-channel SCART is supported.
VI_5
8
The inputs must be ac-coupled. The recommended coupling capacitor is 0.1
F.
VI_6
9
The possible input configurations are listed in the input select register 00h.
VI_7
17
Unused inputs must be connected to ground through 0.1-
F capacitors.
VI_8
18
VI_9
19
VI_10
21
VI_11
22
VI_12
23
Analog_out
127
O
Unbuffered analog video output
Clock Signals
XIN
121
I
External clock reference input. It may connected to external oscillator with 1.8-V compatible
clock signal or 14.31818-MHz crystal oscillator.
XOUT
122
O
External clock reference output. Not connected if XTAL1 is driven by an external
single-ended oscillator.
SCLK
84
O
Line-locked data output clock
Digital Video
Y[9:0]
87
–91,
O
Digital video output of Y/YCbCr, Y_9 is MSB and Y_0 is LSB. For 8-bit operation, the upper
94
–98
8 bits must be connected.
C[9:0] / GPIO
101
–104,
I/O
Digital video output of CbCr, C_9 is MSB and C_0 is LSB. These terminals can be
107
–110,
programmable general purpose I/O, or as digital overlay controls. For 8-bit operation, the
113, 114
upper 8 bits must be connected.
FSO
101
I
Fast-switch overlay between digital RGB and any video input
DB
102
I
Digital BLUE input from overlay device
DG
103
I
Digital GREEN input from overlay device
DR
104
I
Digital RED input from overlay device
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
Miscellaneous Signals
RESETB
36
I
Reset input, active low
PWDN
35
I
Power down input
1 = Power down
0 = Normal mode
GLCO /
83
I/O
Genlock control output (GLCO). Supports the real-time control (RTC) format. This pin can
GPIO / I2CA0
also be configured as a general-purpose I/O (GPIO).
During power on reset this pin is sampled along with pin 82 (I2CA1) as an input to determine
the I2C address the device will be configured to. A 10-k
Ω resistor pulls this either high (to
IOVDD) or low to select between addresses.
GPIO / I2CA1
82
I/O
Programmable general purpose I/O
During power on reset this pin is sampled along with pin 83 (I2CA0) as an input to determine
the I2C address the device will be configured to. A 10-k
Ω resistor pulls this either high (to
IOVDD) or low to select between addresses.
INTREQ
32
O
Interrupt request output (open drain when programmed to be active low)
FSS
119
I
SCART fast switch input
NC
6, 10, 20, 24
N/A
No internal connection. Connect to AGND through 0.1-
F capacitors for future compatibility.
Host Interface
SDA
31
I/O
I2C data bus
SCL
30
I/O
I2C clock input
Copyright
2005–2011, Texas Instruments Incorporated
Introduction
15
focus.ti.com: TVP5160
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