參數(shù)資料
型號(hào): TVP5146M1PFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWERPAD, PLASTIC, QFP-80
文件頁(yè)數(shù): 78/104頁(yè)
文件大?。?/td> 593K
代理商: TVP5146M1PFP
259
2.11.70 VDP Pixel Alignment Register
Subaddress
C2h–C3h
Default
01Eh
Subaddress
7
6
5
4
3
2
1
0
C2h
Pixel alignment [7:0]
C3h
Reserved
Pixel alignment [9:8]
Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync,
where the VDP controller initiates the program from one line standard to the next line standard. For example, the
previous line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the
previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be programmed
before the current settings are required.
The default value is 0x1E and has been tested with every standard supported here. A new value is needed only if
a custom standard is in use.
2.11.71 VDP Line Start Register
Subaddress
D6h
Default
06h
7
6
5
4
3
2
1
0
VDP line start [7:0]
VDP line start [7:0]: Sets the VDP line starting address
This register must be set properly before enabling the line mode registers. VDP processor works only in the VBI region
set by this register and the VDP line stop register at subaddress D7h (see Section 2.11.72).
2.11.72 VDP Line Stop Register
Subaddress
D7h
Default
1Bh
7
6
5
4
3
2
1
0
VDP line stop [7:0]
VDP line stop [7:0]: Sets the VDP stop line address
2.11.73 VDP Global Line Mode Register
Subaddress
D8h
Default
FFh
7
6
5
4
3
2
1
0
Global line mode [7:0]
Global line mode [7:0]: VDP processing for multiple lines set by the VDP start line register at subaddress D6h and
the VDP stop line register at subaddress D7h.
Global line mode register has the same bit definition as the general line mode registers.
General line mode has priority over the global line mode.
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