參數(shù)資料
型號: TVP5146M1PFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWERPAD, PLASTIC, QFP-80
文件頁數(shù): 57/104頁
文件大?。?/td> 593K
代理商: TVP5146M1PFP
240
2.11.35 Output Formatter 1 Register
Subaddress
33h
Default
40h
7
6
5
4
3
2
1
0
Sampling rate
YCbCr code range
CbCr code
Reserved
Output format [2:0]
Sampling rate (changing this bit causes the register settings to be reinitialized):
0 = ITU-R BT.601 sampling rate (default)
1 = Square pixel sampling rate
YCbCr code range:
0 = ITU-R BT.601 coding range (Y ranges from 64 to 940. Cb and Cr range from 64 to 960.)
1 = Extended coding range (Y, Cb, and Cr range from 4 to 1016) (default)
CbCr code:
0 = Offset binary code (2s complement + 512) (default)
1 = Straight binary code (2s complement)
Output format [2:0]:
000 = 10-bit 4:2:2 (2
× pixel rate) with embedded syncs (ITU-R BT.656) (default)
001 = 20-bit 4:2:2 (pixel rate) with separate syncs
010 = Reserved
011 = 10-bit 4:2:2 with separate syncs
100–111= Reserved
NOTE: 10-bit mode is also used for the raw VBI output mode when bit 4 (VBI raw) in the
luminance processing control 1 register at subaddress 06h is set (see Section 2.11.7).
2.11.36 Output Formatter 2 Register
Subaddress
34h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Y[9:0] enable
Reserved
CLK polarity
Clock enable
Y[9:0] enable: Y[9:0] and C[9:0] output enable
0 = Y[9:0] and C[9:0] high impedance (default)
1 = Y [9:0] and C[9:0] active
CLK polarity:
0 = Data clocked out on the falling edge of DATACLK (default)
1 = Data clocked out on the rising edge of DATACLK
Clock enable:
0 = DATACLK outputs are high-impedance (default).
1 = DATACLK outputs are enabled.
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