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參數(shù)資料
| 型號： | TVP5020TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 45/87頁 |
| 文件大小： | 387K |
| 代理商： | TVP5020TQFP |
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2–31
2.11.3
VMI Microcode Read Operation
Data read from indirect register 8E will be read from the TVP5020 program RAM. During the read cycle, the
microprocessor resets, points to location zero in the program, and remains reset. The microprocessor
requires a clear-reset operation upon completion of the read operation. The host performs the reset by
writing into the 7F register to clear reset and resume microprocessor function. (There is no specific data
to be written into the 7F register; any data will resume microprocessor function)
.
To avoid violating VMI cycle time requirements during the microcode read operation, the host can poll the
cycle complete bit in the VMI status register. This polling shoud be done following the address load cycle
(for indirect register 8Eh). Alternatively, the cycle complete enable bit in the interrupt enable register (indirect
address C1) can be set to generate an interrupt for the host when data from a read cycle is unavailable.
STEP 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode
Register address
0
0
1
0
0
0
1
1
1
0
STEP 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data
Data
Data
Data
Data
Data
Data
Data
Note: Must readdress for each read of incremental data
STEP 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode
Register address
0
0
1
0
0
0
1
1
1
0
STEP 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data
Data
Data
Data
Data
Data
Data
dData
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear reset
Register address
0
0
0
1
1
1
1
1
1
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear reset
Dummy data
0
1
Data
Data
Data
Data
Data
Data
Data
Data
2.12 Genlock Control
The frequency control word of the internal color subcarrier digital control oscillator (DCO) and the subcarrier
phase reset bit are transmitted via the GLCO terminal. The frequency control word is a 23-bit binary number.
The frequency of the DCO can be calculated from the following equation:
Fctrl
223
×
Fsclk
Where F
dco
is the frequency of the DCO, F
ctrl
is the 23-bit DCO frequency control, and F
sclk
is the frequency
of the SCLK.
Fdco
The last bit (bit 0) of the DCO frequency control is always 0.
A write of 1 to bit 4 of the chrominance control register at host port subaddress 1Ah causes the subcarrier
DCO phase reset bit to be sent on the next scan line on GLCO. The active low reset bit occurs 8 SCLKs
after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the
phase of the TVP5020 internal subcarrier DCO is reset to zero.
A genlocking slave device connected to the GLCO terminal can use the information on GLCO to synchronize
its internal color DCO to achieve clean line and color lock.
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相關代理商/技術參數(shù) |
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| TVP5021PFP | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5021PFPG4 | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5031 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Color Decoder Circuit |
| TVP5031PFP | 功能描述:IC 9-BIT VIDEO DECODER 80-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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