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參數(shù)資料
| 型號(hào)： | TVP5020TQFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | NTSC/PAL VIDEO DECODER |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 15/87頁 |
| 文件大?。?/td> | 387K |
| 代理商： | TVP5020TQFP |
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2–1
2 Detailed Description
2.1
Analog Video Processors and A/D Converter
Figure 2–1 is a functional diagram of the TVP5020 analog video processors and A/D converter. This block
accepts up to two inputs and performs analog signal conditioning (i.e., video clamping, video amplifying),
and carries out analog-to-digital conversion.
2.1.1
Two high-impedance video inputs are sources for a single internal analog channel in the TVP5020. The user
can connect the two analog video inputs to two selectable individual composite video inputs.
Video Input Selection
2.1.2
The internal clamp circuit restores the ac-coupled video signals to a fixed dc level before A/D conversion.
The clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference voltage.
The circuit has two modes of clamping, coarse and fine. In coarse mode, the most negative portion of the
signal (typically the sync tip) is clamped to a fixed dc level. The circuit uses fine mode to prevent spurious
level shifting caused by noise that is more negative than the sync tip on the input signal. When fine mode
is enabled, after the sync position is detected, clamping is only enabled during the sync period.
Analog Input Clamping and Automatic Gain Control Circuits
Input video signal amplitudes may vary significantly from the nominal level of 1 Vpp. An automatic gain
control (AGC) circuit adjusts the signal amplitude to use the maximum range of the A/D converter without
clipping.
The AGC circuit adjusts the signal amplitude based on the detected amplitude of the sync portion of the input
signal. Signal peaks may be present on nonstandard signals that cause clipping at the A/D converter after
gain adjustment based only on sync amplitude. In these cases, the signal will be attenuated before A/D
conversion.
Clamp
Clamp and AGC
Control Logic
Sync Processor
Amplifier
Input Multiplexer
A/D
VI_1A
VI_1B
Analog Input Video
Digitized Video
Channel 1 (0–7)
Figure 2–1. Analog Video Processors and A/D Converters
2.1.3
The TVP5020 contains one 8-bit A/D converter which digitizes the selected analog video signal input. To
prevent high frequencies which are above half of the sampling rate from entering into the system, video
inputs may require external anti-aliasing low pass filters.
2.2
Digital Processing
Figure 2–2 is a block diagram of the TVP5020 digital video processing. This block receives digitized
composite or signals from the A/D converter, and performs Y/C separation, chroma demodulation, and
Y-signal enhancements. It also generates the horizontal and vertical syncs. The YUV digital output may be
programmed into various formats: 16-bit or 8-bit 4:2:2, 12-bit 4:1:1 and ITU-R BT.656 parallel interface
standard. The circuit uses comb filters to reduce the cross-chroma and cross-luma noise.
A/D Converter
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