參數(shù)資料
型號(hào)： TSC251G2DXXX-L16CED
英文描述： IC CYCLONE III FPGA 80K 780FBGA
中文描述： 微控制器
文件頁(yè)數(shù)： 37/63頁(yè)
文件大小： 878K
代理商： TSC251G2DXXX-L16CED
Rev. A - May 7, 1999
37
TSC80251G2D
Notes:
1. Under steady-state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:.............................................10 mA
Maximum I
OL
per 8-bit port:
Port 0.................26 mA
Ports 1-3............15 mA
Maximum Total I
OL
for all:
Output Pins .......71 mA
If I
exceeds the test conditions, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2, and
3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from high to low. In
applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt Trigger or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 causes the V
OH
on ALE and PSEN# to drop below the specification when the address lines are stabilizing.
4. Typical values are obtained using V
DD
= 3 V and T
A
= 25
°
C. They are not tested and there is not guarantee on these values.
5. The input threshold voltage of SCL and SDA meets the I
2
C specification, so an input voltage below 0.3·V
DD
will be recognized as a logic
0 while an input voltage above 0.7·V
DD
will be recognized as a logic 1.
Note:
1.
The clock prescaler is not used: F
OSC
= F
XTAL
.
Figure 12. I
DD
/I
DL
Versus X
TAL
Frequency; V
DD
= 2.7 to 3.6 V
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
15
10
5
0
I
D
/
D
Frequency at X
TAL(1)
(MHz)
2
4
6
8
14
10
12
16
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