參數(shù)資料
型號： TSC251G2DXXX-L16CED
英文描述： IC CYCLONE III FPGA 80K 780FBGA
中文描述： 微控制器
文件頁數(shù)： 16/63頁
文件大小： 878K
代理商： TSC251G2DXXX-L16CED
Rev. A - May 7, 1999
16
TSC80251G2D
7. Instruction Set Summary
This section contains tables that summarize the instruction set. For each instruction there is a short description, its
length in bytes, and its execution time in states (one state time is equal to two system clock cycles). There are
two concurrent processes limiting the effective instruction throughput:
G
Instruction Fetch
G
Instruction Execution
Table 20 to Table 34 assume code executing from on-chip memory, then the CPU is fetching 16-bit at a time and
this is never limiting the execution speed.
If the code is fetched from external memory, a pre-fetch queue will store instructions ahead of execution to optimize
the memory bandwidth usage when slower instructions are executed. However, the effective speed may be limited
depending on the average size of instructions (for the considered section of the program flow). The maximum
average instruction throughput is provided by Table 14 depending on the external memory configuration (from
Page Mode to Non-Page Mode and the maximum number of wait states). If the average size of instructions is not
an integer, the maximum effective throughput is found by pondering the number of states for the neighbor integer
values.
Table 14. Minimum Number of States per Instruction for given Average Sizes
If the average execution time of the considered instructions is larger than the number of states given by Table 14,
this larger value will prevail as the limiting factor. Otherwise, the value from Table 14 must be taken. This is
providing a fair estimation of the execution speed but only the actual code execution can provide the final value.
7.1 Notation for Instruction Operands
Table 15 to Table 19 provide notation for Instruction Operands.
Table 15. Notation for Direct Addressing
Table 16. Notation for Immediate Addressing
Average size of
Instructions
(bytes)
Page Mode
(states)
Non-Page Mode (states)
0 Wait State
1 Wait State
2 Wait States
3 Wait States
4 Wait States
1
1
2
3
4
5
6
2
2
4
6
8
10
12
3
3
6
9
12
15
18
4
4
8
12
16
20
24
5
5
10
15
20
25
30
Direct Address
Description
C251
C51
dir8
A direct 8-bit address. This can be a memory address (00h-7Fh) or a SFR address (80h-
FFh). It is a byte (default), word or double word depending on the other operand.
dir16
A 16-bit memory address (00:0000h-00:FFFFh) used in direct addressing.
Immediate
Address
Description
C251
C51
#data
An 8-bit constant that is immediately addressed in an instruction
#data16
A 16-bit constant that is immediately addressed in an instruction
#0data16
#1data16
A 32-bit constant that is immediately addressed in an instruction. The upper word is filled
with zeros (#0data16) or ones (#1data16).
#short
A constant, equal to 1, 2, or 4, that is immediately addressed in an instruction.
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