參數(shù)資料
型號(hào)： TSC251G2DXXX-L16CED
英文描述： IC CYCLONE III FPGA 80K 780FBGA
中文描述： 微控制器
文件頁數(shù)： 12/63頁
文件大?。?/td> 878K
代理商： TSC251G2DXXX-L16CED
12
Rev. A - May 7, 1999
TSC80251G2D
Table 8. Event Waveform Control SFRs
Table 9. System Management SFRs
Table 10. Interrupt SFRs
Table 11. Keyboard Interface SFRs
Mnemonic
Name
Mnemonic
Name
CCON
EWC-PCA Timer/Counter Control
CCAP0L
EWC-PCA Compare Capture Module 0 Low Register
CMOD
EWC-PCA Timer/Counter Mode
CCAP1L
EWC-PCA Compare Capture Module 1 Low Register
CL
EWC-PCA Timer/Counter Low Register
CCAP2L
EWC-PCA Compare Capture Module 2 Low Register
CH
EWC-PCA Timer/Counter High Register
CCAP3L
EWC-PCA Compare Capture Module 3 Low Register
CCAPM0
EWC-PCA Timer/Counter Mode 0
CCAP4L
EWC-PCA Compare Capture Module 4 Low Register
CCAPM1
EWC-PCA Timer/Counter Mode 1
CCAP0H
EWC-PCA Compare Capture Module 0 High Register
CCAPM2
EWC-PCA Timer/Counter Mode 2
CCAP1H
EWC-PCA Compare Capture Module 1 High Register
CCAPM3
EWC-PCA Timer/Counter Mode 3
CCAP2H
EWC-PCA Compare Capture Module 2 High Register
CCAPM4
EWC-PCA Timer/Counter Mode 4
CCAP3H
EWC-PCA Compare Capture Module 3 High Register
CCAP4H
EWC-PCA Compare Capture Module 4 High Register
Mnemonic
Name
Mnemonic
Name
PCON
Power Control
CKRL
Clock Reload
POWM
Power Management
WCON
Synchronous Real-Time Wait State Control
Mnemonic
Name
Mnemonic
Name
IE0
Interrupt Enable Control 0
IPL0
Interrupt Priority Control Low 0
IE1
Interrupt Enable Control 1
IPH1
Interrupt Priority Control High 1
IPH0
Interrupt Priority Control High 0
IPL1
Interrupt Priority Control Low 1
Mnemonic
Name
Mnemonic
Name
P1IE
Port 1 Input Interrupt Enable
P1LS
Port 1 Level Selection
P1F
Port 1 Flag
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