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參數(shù)資料
| 型號： | TSC251G2DXXX-24IB |
| 英文描述： | IC CYCLONE III FPGA 80K 780FBGA |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 30/63頁 |
| 文件大?。?/td> | 878K |
| 代理商： | TSC251G2DXXX-24IB |
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Rev. A - May 7, 1999
30
TSC80251G2D
8.3 Signature Bytes
The TSC80251G2D derivatives contain factory-programmed Signature Bytes. These bytes are located in non-volatile
memory outside the memory address space at 30h, 31h, 60h and 61h. To read the Signature Bytes, perform the
procedure described in section 8.5, using the verify signature mode (see Table 39). Signature byte values are listed
in Table 37.
Table 37. Signature Bytes (Electronic ID)
8.4 Programming Algorithm
Figure 9 shows the hardware setup needed to program the TSC87251G2D EPROM/OTPROM areas:
G
The chip has to be put under reset and maintained in this state until the completion of the programming sequence.
G
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
G
Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in
this state until the completion of the programming sequence (see below).
G
The voltage on the EA# pin must be set to V
DD
.
G
The programming mode is selected according to the code applied on Port 0 (see Table 38). It has to be applied
until the completion of this programming operation.
G
The programming address is applied on Ports 1 and 3 which are respectively the Most Significant Byte (MSB)
and the Least Significant Byte (LSB) of the address.
G
The programming data are applied on Port 2.
G
The EPROM Programming is done by raising the voltage on the EA# pin to V
PP
, then by generating a low
level pulse on ALE/PROG# pin.
G
The voltage on the EA# pin must be lowered to V
DD
before completing the programming operation.
G
It is possible to alternate programming and verifying operation (See Paragraph 8.5). Please make sure the
voltage on the EA# pin has actually been lowered to V
DD
before performing the verifying operation.
G
PSEN# and the other control signals have to be released to complete a sequence of programming operations
or a sequence of programming and verifying operations.
Signature Address
Signature Data
Vendor
T
EMIC
30h
58h
Architecture
C251
31h
40h
Memory
32 Kbytes EPROM or OTPROM
60h
F7h
32 Kbytes MaskROM or ROMless
77h
Revision
TSC80251G2D derivative
61h
FDh
相關(guān)PDF資料 |
PDF描述 |
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| TSC251G2DXXX-L16CB | IC CYCLONE III FPGA 80K 780FBGA |
| TSC251G2DXXX-L16CED | IC CYCLONE III FPGA 80K 780FBGA |
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