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| 型號(hào)： | TSC251G2DXXX-24IB |
| 英文描述： | IC CYCLONE III FPGA 80K 780FBGA |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 19/63頁 |
| 文件大?。?/td> | 878K |
| 代理商： | TSC251G2DXXX-24IB |
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19
Rev. A - May 7, 1999
TSC80251G2D
Table 21. Summary of Increment and Decrement Instructions
Notes:
1. A shaded cell denotes an instruction in the C51 Architecture.
2. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
Table 22. Summary of Compare Instructions
Notes:
1. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
2. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
3. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Increment
Increment
Decrement
Decrement
INC <dest>
INC <dest>, <src>
DEC <dest>
DEC <dest>, <src>
dest opnd
←
dest opnd + 1
dest opnd
←
dest opnd + src opnd
dest opnd
←
dest opnd - 1
dest opnd
←
dest opnd - src opnd
Mnemonic
<dest>, <src>
(1)
Comments
Binary Mode
Source Mode
Bytes
States
Bytes
States
INC
DEC
A
ACC by 1
1
1
1
1
Rn
Register by 1
1
1
2
2
dir8
Direct address (on-chip RAM or SFR) by 1
2
2
(2)
2
2
(2)
@Ri
Indirect address by 1
1
3
2
4
INC
DEC
Rm, #short
Byte register by 1, 2, or 4
3
2
2
1
WRj, #short
Word register by 1, 2, or 4
3
2
2
1
INC
DRk, #short
Double word register by 1, 2, or 4
3
4
2
3
DEC
DRk, #short
Double word register by 1, 2, or 4
3
5
2
4
INC
DPTR
Data pointer by 1
1
1
1
1
Compare
CMP <dest>, <src>
dest opnd - src opnd
Mnemonic
<dest>, <src>
(2)
Comments
Binary Mode
Source Mode
Bytes
States
Bytes
States
CMP
Rmd, Rms
Register with register
3
2
2
1
WRjd, WRjs
Word register with word register
3
3
2
2
DRkd, DRks
Dword register with dword register
3
5
2
4
Rm, #data
Register with immediate data
4
3
3
2
WRj, #data16
Word register with immediate 16-bit data
5
4
4
3
DRk, #0data16
Dword register with zero-extended 16-bit immediate data
5
6
4
5
DRk, #1data16
Dword register with one-extended 16-bit immediate data
5
6
4
5
Rm, dir8
Direct address (on-chip RAM or SFR) with byte register
4
3
(1)
3
2
(1)
WRj, dir8
Direct address (on-chip RAM or SFR) with word register
4
4
3
3
Rm, dir16
Direct address (64K) with byte register
5
3
(2)
4
(3)
3
(2)
4
(2)
4
2
(2)
3
(3)
2
(2)
3
(2)
WRj, dir16
Direct address (64K) with word register
5
4
Rm, @WRj
Indirect address (64K) with byte register
4
3
Rm, @DRk
Indirect address (16M) with byte register
4
3
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