參數(shù)資料
型號: TS83102G0BMGS
廠商: ATMEL CORP
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: HERMATIC, CI-CGA-152
文件頁數(shù): 45/52頁
文件大?。?/td> 1548K
代理商: TS83102G0BMGS
5
5360A–BDC–06/05
TS83102G0BMGS
Clock Inputs
Logic common mode compatibility for clock inputs
Differential ECL to LVDS
Clock inputs common voltage range (VCLK or VCLKB) (DC
coupled clock input)
AC coupled for LVDS compatibility (common mode 1.2V)
4V
CM
-1.2
0
0.3
V
Clock input power level (low-phase noise sinewave input)
50
single-ended or 100 differential
4PCLK
-4
0
4
dBm
Clock input swing (single ended; with CLKB = 50
to
GND)
4V
CLK
±200
±320
±500
mV
Clock input swing (differential voltage) - on each clock
input
4
V
CLK
VCLKB
±141
±226
±354
mV
Clock input capacitance (die)
4
CCLK
0.3
pF
Clock input resistance
- single-ended
- differential ended
RCLK
45
90
50
100
55
110
Digital Inputs (SDAEN, PGEB, DECB/Diode, B/GB,
DRRB)
4
VIL
VIH
-5
-2
-3
0
V
Digital Inputs (DRRB only)
Logic compatibility
Negative ECL
- logic low
- logic high
4
VIL
V
IH
-1.810
-1.165
-1.625
-0.880
V
Digital Outputs (1)
Logic compatibility (depending on V
PLUSD value)
Differential ECL (V
PLUSD = -0.8 V typical)
Output levels
50
transmission lines, 10 (2 x 50) differentially
terminated
- logic low
- logic high
- swing (each single-ended output)
- common mode
1
4
VOL
V
OH
V
OH - VOL
-0.98
200
-0.95
-1.17
-0.94
230
-1.05
-1.10
300
-1.15
V
mV
V
3.3
Electrical Operating Characteristics (Continued)
V
CC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are independent of VPLUSD common mode
voltage and performances are guaranteed within the limits of the specified V
PLUSD range (from -0.9V to 1.7V);
V
EE = DVEE = -5V; VIN - VINB = 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven.
Parameter
Test
Level
Symbol
Min
Typ
Max
Unit
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