參數(shù)資料
型號(hào)： TPU3035
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
英文描述： CONNECTOR ACCESSORY
中文描述： 連接器附件
文件頁數(shù)： 49/73頁
文件大?。?/td> 1183K
代理商： TPU3035
TPU 3035, TPU 3040
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
49
4.15. I/O Page Definition
Most hardware related functions of the TPU 3040 are
controlled by memory mapped I/O of the 65C02. The fol-
lowing table lists all available registers. For a more de-
tailed description of the I/O page registers see next sec-
tion.
The application software has access to the I/O page reg-
isters via I
2
C-bus using the CPU subaddresses SUB1
and SUB 2.
Reset values are written by TPU during initialization. Ap-
plication software should only write into registers with
user label ‘Appl’!
Most of the I/O page registers are only write registers
and will not return useful data when read by application
software.
Table 4–22:
I/O Page Register
Addr.
Mode
User
Reset
Name
0200 H
R/W
Test
00 H
Control Register
0201 H
W
Test
00 H
Test Mode
0202 H
W
Appl
00 H
Standby
0203 H
W
TPU
6C H
Watchdog
0204 H
R/W
Test
07 H
Supervision
0210 H
R/W
TPU
–
Interface Data
0211 H
R/W
TPU
00 H
Interface Status
0212 H
R
TPU
–
Interface Address
0213 H
W
Appl
01 H
Interface Mode
0220 H
R/W
TPU
FF H
Interrupt Source
0221 H
W
TPU
3B H
Interrupt Enable
0222 H
W
Appl
0F H
Interrupt & Timer Mode
0223 H
R
Appl
–
Timer Latch Low
0224 H
R
Appl
–
Timer Latch High
0225 H
R
Appl
–
Timer Count Low
0226 H
R
Appl
–
Timer Count High
0250 H
W
Appl
04 H
Clamping Start
0251 H
W
Appl
07 H
Blanking Stop
0252 H
W
Appl
00 H
Blanking Start
0253 H
W
Appl
37 H
Halfline Code
0254 H
W
Appl
60 H
Display Mode 1
0255 H
W
Appl
4D H
Display Mode 2
0256 H
W
Appl
07 H
Clamping Stop
025A H
W
Appl
35 H
PRIO Mode
025B H
R/W
Appl
00 H
FB Mode
0260 H
W
Appl
0060 H
OSD Layer Vertical Start
0261 H
W
Appl
0128 H
OSD Layer Vertical Stop
0262 H
W
Appl
16 H
OSD Layer Horizontal Start
0264 H
W
Appl
version
OSD Layer Text Pointer
0265 H
W
Appl
0138 H
OSD Layer 2nd Color Start
0266 H
W
Appl
0C H
OSD Layer 2nd Color
0267 H
W
Appl
0024 H
WST Layer Vertical Start
0268 H
W
Appl
0F H
WST Layer Horizontal Start
0269 H
W
Test
00 H
OSD Test
026A H
W
Appl
0128 H
WST Layer Vertical Stop
026B H
W
Appl
011E H
WST Layer Last Row
026C H
W
Appl
00 H
RGB Mode
026D H
W
Appl
00 H
Sync Mode
026E H
W
TPU
pal font
Display Font Pointer
026F H
W
Appl
8F H
Display Mode 3
0270 H
W
TPU
00 H
Display Mode 4
Addr.
Mode
User
Reset
Name
0271 H
W
Test
00 H
Display Test 1
0272 H
W
Test
00 H
Display Test 2
0273 H
W
TPU
00 H
Display Mode 5
0274 H
W
Test
00 H
Display Test 4
0280 H
R/W
TPU
00 H
DRAM Display Pointer Low
0281 H
R/W
TPU
20 H
DRAM Display Pointer Medium
0282 H
R/W
TPU
00 H
DRAM Display Pointer High
0283 H
R/W
TPU
00 H
DRAM Slicer Pointer Low
0284 H
R/W
TPU
10 H
DRAM Slicer Pointer Medium
0285 H
R/W
TPU
00 H
DRAM Slicer Pointer High
0286 H
R/W
TPU
–
DRAM CPU Write Pointer Low
0287 H
R/W
TPU
–
DRAM CPU Write Pointer Medium
0288 H
R/W
TPU
–
DRAM CPU Write Pointer High
0289 H
R/W
TPU
–
DRAM CPU Read Pointer Low
028A H
R/W
TPU
–
DRAM CPU Read Pointer Medium
028B H
R/W
TPU
–
DRAM CPU Read Pointer High
028C H
R/W
TPU
–
DRAM Data
028D H
R/W
TPU
–
DRAM Hamming Data
028E H
W
TPU
06 H
DRAM Mode
0290 H
W
TPU
01 H
ACQ Soft Slicer
0291 H
W
Appl
BE H
ACQ TTX Bitslicer Frequency Low
0292 H
W
Appl
0A H
ACQ TTX Bitslicer Frequency High
0293 H
W
Appl
FA H
ACQ VPS Bitslicer Frequency Low
0294 H
W
Appl
09 H
ACQ VPS Bitslicer Frequency High
0295 H
W
TPU
07 H
ACQ Filter Coefficient
0296 H
W
TPU
0D H
ACQ Data Slicer
0297 H
W
TPU
04 H
ACQ Accumulator Mode
0298 H
R
TPU
–
ACQ AC Accumulator
0299 H
R
TPU
–
ACQ FLT Accumulator
029A H
W
Test
00 H
ACQ Packet Header Low
029B H
W
Test
00 H
ACQ Packet Header High
029C H
R
TPU
–
ACQ Soft Error Counter
029D H
W
TPU
0F H
ACQ Sync Slicer
029E H
R
Appl
–
ACQ Sync Status
029F H
W
Appl
18 H
ACQ Standard
02A0 H
W
TPU
50 H
ACQ Analog Mode
02A1 H
W
Test
00 H
ACQ Test Mode
02A2 H
W
Test
00 H
ACQ Test Observe
02A3 H
W
Appl
00 H
ACQ Video Input
02A4 H
R
Appl
–
ACQ HSync Counter
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