
TPU 2735
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12. Description of the IM Bus
The INTERMETALL Bus (IM Bus for short) was de-
signed to control the DIGIT 2000 ICs by the CCU Central
Control Unit. Via this bus the CCU can write data to the
ICs or read data from them. This means the CCU acts
as a master whereas all controlled ICs are slaves.
The IM Bus consists of three lines for the signals Ident
(ID), Clock (CL) and Data (D). The clock frequency
range is 50Hz to 170 kHz. Ident and clock are unidirec-
tional from the CCU to the slave ICs, Data is bidirec-
tional. Bidirectionality is achieved by using open-drain
outputs with on-resistances of 150
maximum. The 2.5
k
pull-up resistor common to all outputs is incorporated
in the CCU.
The timing of a complete IM Bus transaction is shown in
Fig. 12–1 and Table 12–1. In the non-operative state the
signals of all three bus lines are High. To start a transac-
tion the CCU sets the ID signal to Low level, indicating
an address transmission, and sets the CL signal to Low
level as well to switch the first bit on the Data line. There-
after eight address bits are transmitted beginning with
the LSB. Data takeover in the slave ICs occurs at the
positive edge of the clock signal. At the end of the ad-
dress byte the ID signal goes High, initiating the address
comparison in the slave circuits. In the addressed slave
the IM bus interface switches over to Data read or write,
because these functions are correlated to the address.
Also controlled by the address the CCU now transmits
eight or sixteen clock pulses, and accordingly one or two
bytes of data are written into the addressed IC or read
out from it, beginning with the LSB.
The completion of the bus transaction is signalled by a
short low-state pulse of the ID signal. This initiates the
storing of the transferred data.
It is permissible to interrupt a bus transaction for up to
10 ms.