參數(shù)資料
型號: TPU2735
廠商: Electronic Theatre Controls, Inc.
英文描述: Teletext Processor
中文描述: 圖文處理器
文件頁數(shù): 17/37頁
文件大?。?/td> 1019K
代理商: TPU2735
TPU 2735
17
6. Controlling the TPU 2735 with the CCU 2030,
CCU 2050 or CCU 2070
TPU and CCU communicate via the IM bus. The CCU
can read from and write to all RAM locations of the TPU
system and can test the status (ready/busy) of the con-
trol interface of the TPU. The CCU can control the TPU
by addressing the control registers in the RAM.
The TPU 2735 distinguishes the following types of com-
mands:
Command
IM Bus Address
read a 16-bit write address
read a 16-bit read address
8-bit data transfer
(read or write)
status test
hardware test/configuration
7 A (Hex)
7 B (Hex)
7 C (Hex)
7 D (Hex)
7 E (Hex)
Each type of command has its own IM bus address. The
TPU has accomplished a CCU command when the busy
flags are 0.
Every data transfer starts with a TPU status check, i.e.
a read status command with status equal to zero. Next
the read or write address is transferred. After the ad-
dress command another status check is required. The
subsequent data is written to or read from the RAM ac-
cording to the preceding address command. The RAM
address is incremented after each data transfer.
address
check status
data
read next address
(auto increment)
check status
Fig. 6–1:
Command sequence for reading data
from TPU to CCU with optional auto increment
address
check status
data
write next address
(auto increment)
check status
Fig. 6–2:
Command sequence for writing data
from TPU to CCU with optional auto increment
The maximum busy time is 2.5 ms. The test of the inter-
face status can be followed immediately by another
command if the busy flag was low or by a second test if
the busy flag was high.
6.1. The Address Commands
The 16-bit address consists of four parts:
– block address (0 to 3)
2 bits
– sector address (0 to 7)
3 bits
– row address (0 to 25)
5 bits
– column address (0 to 39)
6 bits
Each sector defines the memory locations for a Teletext
page and consists of 25 rows. The rows 0 to 24 can be
used as display memory, row 24 and row 25 can be used
as control registers. The row and column addresses cor-
respond to the position of the character display on the
screen. The data format of the address (C
0
being trans-
mitted first) is:
C
5 ...
C
0
...
block
address
MSB
sector
address
row
address
column
address
LSB
B
1
B
0
S
2
S
1
S
0
R
4
R
0
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