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參數(shù)資料
| 型號： | TPU2735 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Teletext Processor |
| 中文描述： | 圖文處理器 |
| 文件頁數(shù)： | 18/37頁 |
| 文件大小： | 1019K |
| 代理商： | TPU2735 |
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TPU 2735
18
6.2. The Data Transfer Command
A data command transfers 8 bits of data from the CCU
to the TPU or vice versa. The transfer direction depends
on the type of the last address command before the data
transfer command. A data transfer command following
a read address command makes the TPU answer with
8 bits of data. The LSB is transmitted first.
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
The RAM address of subsequent data transfer com-
mands is automatically incremented by 1. However, the
sector address is not incremented on row address over-
flow.
Read Address Command
Write Address Command
Data Transfer
Command
RAM Address
Busy 1
Busy 2
N
1
N
1
+1 N
1
+2
N
1
+3
N
2
N
2
+1
Fig. 6–3:
Example of a Read/Write command
sequence
6.3. The Status Test Command
The TPU answers to this command with an 8-bit status
word:
0
0
0
0
0
0
BUI 2 BUI 1
MSB
LSB
The busy flags indicate the status of the interface as fol-
lows:
BUI 1
BUI 2
Interface Status
0
1
1
0
0
1
ready for commands
not ready for commands
ready only for address
commands
6.4. The IM Bus Hardware Test/Configuration
Register
This register allows to control the polarity and the state
of the fast blank input signal. The register is write only
and is cleared with hardware reset. All unused bits must
be set to zero.
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
FBP
FBO
0
0
FBP:
0 active low (compatible with TPU 2732)
1 active high
Fast Blank Polarity:
FBO:
0 no action
1 set Fast Blank to 1 (internally) – in this state FBP allows
to switch the FB signal under program control.
Fast Blank Overwrite:
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