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APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1
μ
F to 1.0
μ
F low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection,
and
ripple
rejection.
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or if the device is not
located near the power source. If source impedance
is not sufficiently low, a 0.1
μ
F input capacitor may be
necessary to ensure stability.
TPS728xx
GND
EN
VSET
IN
OUT
V
IN
V
OUT
1 F
m
1 F
m
2.7V to 6.5V
0.9V to 3.6V
On
Off
On (V
)
OUT2
Off (V
)
OUT1
APPLICATION EXAMPLES
EEPROM-based
programming voltage to be higher than the operating
voltage. The TPS728xx suits such applications where
the maximum programming voltage of the EEPROM
is higher than the operating voltage. The VSET logic
pin allows the application to transition between the
higher EEPROM programming voltage and the lower
operating
voltage.
For
typically takes less than 40
μ
s to transition from a
lower voltage of 1.85V to a higher voltage of 3.15V
under an output load of 1mA to 10mA, as shown in
Figure 35
and
Figure 37
, respectively. The special
circuitry in the TPS728xx helps transition from the
higher voltage to the lower voltage under no load.
The load on the output at the end of the programming
cycle
is
typically
under
overshoots and undershoots are minimal under this
load condition. The TPS728xx typically takes less
than 1ms of transition time going from 3.15V to
1.85V, as shown in
Figure 36
and
Figure 38
,
respectively. Both output states of the TPS728xx are
programmable between 0.9V to 3.6V.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for V
IN
and V
OUT
, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the output capacitor should
connect directly to the GND pin of the device. High
ESR capacitors may degrade PSRR.
TPS728xx Series
SBVS095–AUGUST 2007
Another area where the TPS728xx can be used
effectively is in dynamic voltage scaling (DVS)
applications. In DVS applications, it is required to
dynamically
switch
between
voltage to a low standby voltage in order to balance
performance
of
processors
savings. Modern multimillion gate microprocessors
fabricated with the latest sub-micron processes save
on power by transitioning to a lower voltage to reduce
leakage
currents
without
architecture enables the microprocessor to transition
quickly into an operational state (wake up) without
requiring
reloading
of
the
memory, or a reboot.
The TPS728xx series belongs to a family of new
generation
LDO
regulators
circuitry to achieve ultra-wide bandwidth and high
loop gain, resulting in extremely high PSRR (up to
1MHz) at very low headroom (V
IN
– V
OUT
). These
features, combined with low noise, low ground pin
current, and ultra-small packaging, make this device
ideal
for
portable
applications.
regulators
offers
sub-bandgap
current limit and thermal protection, and is fully
specified from –40
°
C to +125
°
C.
Figure 39
shows the basic circuit connections.
that
use
innovative
a
high
operational
and
achieve
power
This
output
family
voltages,
of
losing
content.
This
states
from
external
A
higher-value
Figure 39. Typical Application Circuit
The TPS728xx is designed to be stable with standard
ceramic capacitors with values of 1.0
μ
F or larger at
the output. X5R- and X7R-type capacitors are best
because they have minimal variation in value and
ESR over temperature. Maximum ESR should be less
than 1.0
.
applications
require
the
example,
the
TPS728xx
10mA.
Output
voltage
Copyright 2007, Texas Instruments Incorporated
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