參數(shù)資料
型號(hào)： TPS728XX
廠商： Texas Instruments, Inc.
英文描述： 200mA Low-Dropout Linear Regulator with Pin-Selectable Dual-Voltage Level Output
中文描述： 200mA低與品差線性穩(wěn)壓器可選雙電壓電平輸出
文件頁數(shù)： 14/22頁
文件大小： 763K
代理商： TPS728XX
www.ti.com
INTERNAL CURRENT LIMIT
The TPS728xx internal current limits help protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of output voltage. For reliable
operation, the device should not be operated in a
current limit state for extended periods of time.
TPS728xx
GND
EN
VSET
IN
OUT
V
IN
V
OUT
1 F
m
1 F
m
2.7V to 6.5V
0.9V to 3.6V
VSET2
VSET1
2k
W
SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to the IN pin, as shown in
Figure 40
.
Figure 41
shows when both EN and VSET are tied to
IN.
The
TPS728xx,
with
pulldown circuitry, discharges the output to within 5%
of V
OUT
with a time (
t
) of:
t = 3
60
60 + R
L
R
L
′
C
OUT
′
TPS728xx
GND
EN
VSET
IN
OUT
V
IN
V
OUT
1 F
m
1 F
m
2.7V to 6.5V
0.9V to 3.6V
2k
W
DROPOUT VOLTAGE
The TPS728xx uses a PMOS pass transistor to
achieve low dropout. When (V
IN
– V
OUT
) is less than
the dropout voltage (V
DO
), the PMOS pass device is
in
the
linear
region
input-to-output resistance is the R
DS(ON)
of the PMOS
pass element. V
DO
approximately scales with output
current because the PMOS device behaves like a
resistor in dropout.
UNDERVOLTAGE LOCK-OUT (UVLO)
The TPS728xx uses an undervoltage lock-out circuit
to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a deglitch
feature
so
that
it
typically
transients on the input if they are less than 5
μ
s
duration. The UVLO circuit triggers at approximately
2.3V on an undershooting or a falling input voltage.
On the TPS728xx, the active pulldown discharges
V
OUT
when the device is in UVLO off condition.
However, the input voltage must be greater than 0.8V
for the active pulldown to work.
MINIMUM LOAD
The
TPS728xx
Traditional PMOS LDO regulators suffer from lower
loop gain at very light output loads. The TPS728xx
employs an innovative, low-current mode circuit
under very light or no-load conditions, resulting in
improved
output
voltage
down to zero output current.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
TPS728xx Series
SBVS095–AUGUST 2007
The PMOS pass element in the TPS728xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of
rated output current may be appropriate.
Figure 40. Circuit Showing EN Tied High when
Shutdown Capability is Not Required
internal
active
output
Where:
Figure 41. Circuit to Tie Both EN and VSET High
R
L
= output load resistance
C
OUT
= output capacitance
of
operation
and
the
ignores
undershoot
As with any linear regulator, PSRR and transient
response are degraded as (V
IN
– V
OUT
) approaches
dropout. This effect is shown in
Figure 25
and
Figure 26
in the
Typical Characteristics
section.
is
stable
with
no
output
load.
regulation
performance
14
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Copyright 2007, Texas Instruments Incorporated
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