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參數(shù)資料
| 型號： | TPS70758PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封裝： | GREEN, PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 918K |
| 代理商： | TPS70758PWPRG4 |
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RESET
VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
VI
VOUT1
MR1
0.1 mF
10 mF
0.1 mF
MR2
EN
TPS707xxPWP
(FixedOutputOption)
>2 V
<0.7 V
250 kW
120ms
EN
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQUENCE
95%
83%
95%
NOTE A: t1 Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
VOUT1 faults out
TPS70745, TPS70748
TPS70751, TPS70758
TPS70702
SLVS291D – MAY 2000 – REVISED DECEMBER 2007
Application condition: VIN1 and VIN2 are tied to the
same fixed input voltage greater than the VUVLO; SEQ
is tied to logic high; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
EN is initially high; therefore, both regulators are off
and PG1 and RESET are at logic low. With SEQ at
logic high, when EN is taken low, VOUT2 turns on.
VOUT1 turns on after VOUT2 reaches 83% of its
regulated output voltage. When VOUT1 reaches 95%
of its regulated output voltage, PG1 (tied to MR2)
goes to logic high. When both VOUT1 and VOUT2 reach
95% of their respective regulated output voltages and
both MR1 and MR2 (tied to PG1) are at logic high,
RESET is pulled to logic high after a 120ms delay.
When a fault on VOUT1 causes it to fall below 95% of
its regulated output voltage, PG1 (tied to MR2) goes
to logic low, causing RESET to return to logic low.
VOUT2 remains on because SEQ is high.
Figure 39. Timing when VOUT1 Faults Out
Copyright 2000–2007, Texas Instruments Incorporated
25
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