參數(shù)資料
型號: TPS70702PWP
廠商: Texas Instruments, Inc.
元件分類: 線性穩(wěn)壓
英文描述: DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
中文描述: 兩用低壓差最多可劈開電壓DSP系統(tǒng)序列電源電壓穩(wěn)壓器的輸出
文件頁數(shù): 22/34頁
文件大?。?/td> 505K
代理商: TPS70702PWP
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 44 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
LDO
VI
VESR
IO
RESR
CO
RLOAD
VO
+
Figure 44. LDO Output Stage With Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into the CO
branch. If IO suddenly increases (transient condition), the following occurs:
The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 45). Therefore,
capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR.
This voltage is shown as VESR in Figure 44.
When CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – VESR. Due to the
discharge of CO, the output voltage VO will drop continuously until the response time t1 of the LDO is reached
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches
the regulated voltage. This period is shown as t2 in Figure 45.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
D The higher the ESR, the larger the droop at the beginning of load transient.
D The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
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