參數(shù)資料
型號： TPS70702PWP
廠商： Texas Instruments, Inc.
元件分類： 線性穩(wěn)壓
英文描述： DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
中文描述： 兩用低壓差最多可劈開電壓DSP系統(tǒng)序列電源電壓穩(wěn)壓器的輸出
文件頁數(shù)： 11/34頁
文件大小： 505K
代理商： TPS70702PWP
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
The TPS707xx low dropout regulator family provides dual regulated output voltages for DSP applications that
require a high-performance power management solution. These devices provide fast transient response and
high accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing
provides a power solution for DSPs without any external component requirements. This reduces the component
cost and board space while increasing total system reliability. TPS707xx family has an enable feature which puts
the device in sleep mode reducing the input currents to less than 3
A. Other features are integrated SVS (power
on reset, RESET) and power good (PG1) that monitor output voltages and provide logic output to the system.
These differentiated features provide a complete DSP power solution.
The TPS707xx, unlike many other LDOs, feature very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is
directly proportional to the load current through the regulator (IB = IC/β). The TPS707xx uses a PMOS transistor
to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the
full load range.
pin functions
enable
The EN terminal is an input which enables or shuts down the device. If EN is at a voltage high signal the device
will be in shutdown mode. When the EN goes to voltage low, then the device will be enabled.
sequence
The SEQ terminal is an input that programs which output voltage (VOUT1 or VOUT2) will be turned on first. When
the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 will turn on first and VOUT1 will
remain off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time the VOUT1 will
be turned on. If VOUT2 is pulled below 83% (i.e., over load condition) VOUT1 will be turned off. This terminal has
a 6-
A pullup current to VIN1.
Pulling the SEQ terminal low reverses the power-up order and VOUT1 will be turned on first. For detail timing
diagrams refer to Figures 36 and 42.
power–good
The PG1 terminal is an open drain, active high output terminal which indicates the status of the VOUT1 regulator.
When the VOUT1 reaches 95% of its regulated voltage, PG1 goes into a high impedance state. PG1 goes into
a low impedance state when VOUT1 is pulled below 95% (i.e. over-load condition) of its regulated voltage. The
open drain output of the PG1 terminal requires a pullup resistor.
manual reset pins (MR1 and MR2)
MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled
to logic low, a POR (RESET) will occur. These terminals have a 6-
A pullup current to VIN1.
sense (VSENSE1, VSENSE2)
The sense terminals of fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers
through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route
the sense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the VSENSE
terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to oscillate.
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and VOUT
terminals to filter noise is not recommended because it can cause the regulators to oscillate.
相關PDF資料
PDF描述
TPS70745PWP DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
TPS70751PWP DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
TPS70758PWPRG4 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20
TPS70802PWP DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
TPS70845PWP DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
相關代理商/技術參數(shù)
參數(shù)描述
TPS70702PWPG4 功能描述:低壓差穩(wěn)壓器 - LDO Dual Adj 1A/2A LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20
TPS70702PWPR 功能描述:低壓差穩(wěn)壓器 - LDO Dual-Output LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20
TPS70702PWPRG4 功能描述:低壓差穩(wěn)壓器 - LDO Dual-Output LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20
TPS70745 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
TPS70745PWP 功能描述:低壓差穩(wěn)壓器 - LDO 3.3V/1.2V 250/125mA RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動電壓（最大值）:307 mV 輸出電流:1 A 負載調節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-20
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