參數(shù)資料
型號： TPS65950ZXNT
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝： 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數(shù)： 128/167頁
文件大?。?/td> 2566K
代理商： TPS65950ZXNT
4.5.4.1 Power-Off Sequence in Master Modes
VBAT
DEVOFF(register)
NRESPWRON
REGEN
32K
OUT
CLK
DCDCs
LDOs
SYSEN
HFCLKOUT
CLKEN
NEXT_Startup_event
18 s
m
1.2ms
18 s
m
18 s
m
18 s
m
3.42msbeforedetectionofstartingevent
126 s
m
032-013
TPS65950
Integrated Power Management/Audio Codec
www.ti.com
SWCS032 – OCTOBER 2008
Figure 4-11 shows the timing and control that occur during the power-off sequence in master modes.
NOTE: All timings are typical values with the default setup (depending on the resynchronization between power domains,
state machinery priority, etc.).
Figure 4-11. Power-Off Sequence in Master Modes
If the value of the HF clock is not 19.2 MHz (with the values of the CFG_BOOT HFCLK_FREQ bit field set
accordingly), the delay between DEVOFF and NRESPWRON/CLK32KOUT/SYSEN/HFCLKOUT is divided
by two (approximately 9
s). This is caused by the internal frequency used by power STM switching from
3 to 1.5 MHz if the HF clock value is 19.2 MHz.
The DEVOFF event is PWRON falling edge in slave mode and DEVOFF internal register write in master
mode.
Power Module
63
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