參數(shù)資料
型號： TPS65950ZXNR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA209
封裝： 7 X 7 MM, 0.40 MM PITCH, PLASTIC, BGA-209
文件頁數(shù)： 59/167頁
文件大?。?/td> 2566K
代理商： TPS65950ZXNR
13.6 JTAG Interfaces
JTAG.TCK
JTAG.TDI
JTAG.TMS
JTAG.TDO
JL1
JL2
JL7
JL3
JL4
JL6
JL5
032-083
TPS65950
Integrated Power Management/Audio Codec
www.ti.com
SWCS032 – OCTOBER 2008
Table 13-10. Voice PCM Interface Switching Characteristics (Mode 1) (continued)
Notation
Parameter
Min(1)
Max(2)
Unit
P2
td(VCK-VFS)
Delay time, PCM.VCK transition to PCM.VFS transition (5)
–10
10 +
ns
Pvoice
P5
td(VCL-VDX)
Delay time, PCM.VCK transition to PCM.VDX transition
–10
10
ns
Voice PCM Slave Mode
P5
td(VCL-VDX)
Delay time, PCM.VCK transition to PCM.VDX transition
0
20
ns
(5)
When TPS65950 is master, the PCM.VFS is delivered one cycle time of 26-MHz voice clock (Pvoice=38.4 ns) after the PCM.VCK rising
edge.
The TPS65950 Joint Test Action Group (JTAG) test access port (TAP) controller handles standard IEEE
JTAG interfaces. This section describes the timing requirements for the tools used to test TPS65950
power management.
The JTAG/TAP module provides a JTAG interface according to IEEE Standard 1149.1a. This interface
uses the four I/O pins TMS, TCK, TDI, and TDO. The TMS, TCK, and TDI inputs contain a pullup device,
which makes their state high when they are not driven. The output TDO is a 3-state output, which is high
impedance except when data are shifted between TDI and TDO:
TCK is the test clock signal.
TMS is the test mode select signal.
TDI is the scan path input.
TDO is the scan path output.
TMS and TDO are multiplexed at the top level with the GPIO0 and GPIO1 pins. The dedicated external
test pin switches from functional mode (GPIO0 and GPIO1) to JTAG mode (TMS and TDO). The JTAG
operations are controlled by a state-machine that follows the IEEE Standard 1149.1a state diagram. This
state-machine is reset by the TPS65950 internal power-on reset (POR). A test mode is selected by writing
a 6-bit word (instruction) into the instruction register and then accessing the related data register.
Table 13-11 and Table 13-12 assume testing over the recommended operating conditions (see
Figure 13-7). The input timing requirements are given by considering a rising or falling edge of 7 ns. The
capacitive load is 35 pF.
Figure 13-7. JTAG Interface Timing
Timing Requirements and Switching Characteristics
151
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