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參數(shù)資料
| 型號(hào)： | TPS3610U18PWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | BATTERY-BACKUP SUPERVISORS FOR RAM RETENTION |
| 中文描述： | 電池備份的RAM保持監(jiān)事 |
| 文件頁(yè)數(shù)： | 14/22頁(yè) |
| 文件大?。?/td> | 453K |
| 代理商： | TPS3610U18PWR |
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SLVS327B
–
DECEMBER 2000
–
REVISED DECEMBER 2002
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements at R
L
= 1 M
, C
L
= 50 pF, T
A
=
–
40
°
C to 85
°
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
s
ns
tw
Pulse width
At VDD
At WDI
VIH = VIT + 0.2 V, VIL = VIT
–
0.2 V
VDD = VIT + 0.2 V, VIL = 0.3
×
VDD, VIH = 0.7
×
VDD
6
100
switching characteristics at R
L
= 1 M
, C
L
= 50 pF, T
A
=
–
40
°
C to 85
°
C
PARAMETER
TEST CONDITIONS
MIN
60
TYP
100
MAX
140
UNIT
ms
td
t(tout)
Delay time
VDD > VIT +0.2 V
(see timing diagram
Watchdog timeout
0.48
0.8
1.12
s
tPLH
Propagation (delay) time, low-to-
high-level output
50% RESET to 50% CEOUT
15
μ
s
VDD = 1.8 V
VDD = 3.3 V
VDD = 5 V
VIL = VIT
–
0.2 V,
VIH = VIT+0.2 V
VIL = V(PFI)
–
0.2 V,
VIH = V(PFI)+0.2 V
VIH = VBAT + 200 mV,
VIL = VBAT
–
200 mV,
VBAT < VIT
5
15
50% CEIN to 50% CEOUT,
CL = 50 pF only (see Note 7)
l (
1.6
5
ns
Propagation (delay) time high-to-
Propagation (delay) time, high-to-
low-level output
1
3
tPHL
VDD to RESET
2
5
PFI to PFO
3
5
μ
s
tt
Transition time
VDD to BATTON
3
μ
s
NOTE 7: Specified by design
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
6
Static drain-source on-state resistance (VDD to VOUT)
Static drain-source on-state resistance (VBAT to VOUT)
Static drain-source on-state resistance
vs Output current
rDS(on)
7
vs Input voltage at CEIN
8
IDD
VIT
Supply current
vs Supply voltage
9
Normalized threshold at RESET
vs Free-air temperature
10
High-level output voltage at RESET
11, 12
VOH
High-level output voltage at PFO
vs High-level output current
vs High level out ut current
13, 14
High-level output voltage at CEOUT
15, 16, 17, 18
Low-level output voltage at RESET
19, 20
VOL
Low-level output voltage at CEOUT
vs Low-level output current
vs Low level out ut current
21, 22
Low-level output voltage at BATTON
23, 24
tp(min)
tp(min)
Minimum Pulse Duration at VDD
Minimum Pulse Duration at PFI
vs Threshold overdrive at VDD
vs Threshold overdrive at PFI
25
26
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| TPS3610U18PWRG4 | 功能描述:監(jiān)控電路 Battery-Backup for RAM Retention RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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