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參數(shù)資料
| 型號(hào)： | TPS3307-33Y |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRIPLE PROCESSOR SUPERVISORS |
| 中文描述： | 三重處理器監(jiān)事 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 430K |
| 代理商： | TPS3307-33Y |
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FUNCTION/TRUTH TABLES
TPS3307-18, TPS3307-25, TPS3307-33
SLVS199B–DECEMBER 1998–REVISED OCTOBER 2004
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system
reset. The delay time, t
d (typ)
= 200ms, starts after all SENSE
n
inputs have risen above the threshold voltage V
IT+
.
When the voltage at any SENSE input drops below the threshold voltage V
IT-
, the RESET output becomes active
(low) again.
The TPS3307-xx family of devices incorporates a manual reset input, MR. A low level at MR causes RESET to
become active. In addition to the active-low RESET output, the TPS3307-xx family includes an active-high
RESET output.
The devices are available in either 8-pin MSOP or standard 8-pin SO packages.
The TPS3307-xx devices are characterized for operation over a temperature range of –40
°
C to 85
°
C.
SUPPLY VOLTAGE MONITORING
NOMINAL SUPERVISED VOLTAGE
THRESHOLD VOLTAGE (TYP)
DEVICE
SENSE1
SENSE2
SENSE3
SENSE1
SENSE2
SENSE3
TPS3307-18
3.3V
1.8V
User defined
2.93V
1.68V
1.25V
(1)
TPS3307-25
3.3V
2.5V
User defined
2.93V
2.25V
1.25V
(1)
TPS3307-33
5V
3.3V
User defined
4.55V
2.93V
1.25V
(1)
(1)
The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements.
AVAILABLE OPTIONS
PACKAGED DEVICES
MARKING
DGN PACKAGE
CHIP FORM
(Y)
PowerPAD
μ-SMALL OUTLINE
(DGN)
TPS3307-18DGN
TPS3307-25DGN
TPS3307-33DGN
T
A
SMALL OUTLINE
(D)
TPS3307-18D
TPS3307-25D
TPS3307-33D
TIAAP
TIAAQ
TIAAR
TPS3307-18Y
TPS3307-25Y
TPS3307-33Y
-40
°
C to 85
°
C
MR
L
H
H
H
H
H
H
H
H
SENSE1 > V
IT1
X
(1)
0
0
0
0
1
1
1
1
SENSE2 > V
IT2
X
(1)
0
0
1
1
0
0
1
1
SENSE3 > V
IT3
X
0
1
0
1
0
1
0
1
RESET
L
L
L
L
L
L
L
L
H
RESET
H
H
H
H
H
H
H
H
L
(1)
X = Don't care
2
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