參數(shù)資料
型號(hào): TPS23841_07
廠商: Texas Instruments, Inc.
英文描述: HIGH-POWER, WIDE VOLTAGE RANGE, QUAD-PORT ETHERNET POWER SOURCING EQUIPMENT MANAGER
中文描述: 大功率,寬電壓范圍,四端口以太網(wǎng)供電設(shè)備管理器
文件頁數(shù): 30/52頁
文件大?。?/td> 1011K
代理商: TPS23841_07
www.ti.com
Chip Addressing
Port/Register Cycle
Data Write Cycle
TPS23841
SLUS745–NOVEMBER 2006
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued)
Table 1
shows the bit assignments during the addressing cycle.
Table 1. Address Selection Field
BIT
A7
A6
A5
A4
A3
A2
A1
A0
FUNCTION
Future expansion (value not compared)
Future expansion (value not compared)
Device address. Compared with pin A5
Device address. Compared with pin A4
Device address. Compared with pin A3
Device address. Compared with pin A2
Device address LSB. Compared with pin A1
Read/Write
After the chip address cycle, the TPS23841 accepts eight bits of port/register select data as defined in
Table 2
.
The SCL line high-to-low transition after the eighth data bit then latches the selection of the appropriate internal
register for the follow-on data read or write operation. After latching the eight-bit data field, the TPS23841 pulls
the SDA_O line low for one clock cycle, for the acknowledge pulse.
For a data write sequence, after the Port/Register address cycle, the TPS23841 accepts the eight bits of data as
defined in the tables below. The data is latched into the previously selected Write Register, and the TPS23841
generates a data acknowledge pulse by pulling the SDA_O line low for one clock cycle. Common register
functions act on all ports simultaneously. Per port registers are specific to the target port only.
To reset the interface, the host or master subsequently generates a stop bit by releasing the SDA_I line during
the clock-high portion of an SCL pulse.
30
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