參數(shù)資料
型號(hào): TPS23841_07
廠商: Texas Instruments, Inc.
英文描述: HIGH-POWER, WIDE VOLTAGE RANGE, QUAD-PORT ETHERNET POWER SOURCING EQUIPMENT MANAGER
中文描述: 大功率,寬電壓范圍,四端口以太網(wǎng)供電設(shè)備管理器
文件頁(yè)數(shù): 28/52頁(yè)
文件大?。?/td> 1011K
代理商: TPS23841_07
www.ti.com
I
2
C Interface Description
The serial interface used in the TPS23841 is a standard 2-wire I
2
C slave architecture. The standard SDA line of
the I
2
C architecture is broken out into independent input and output data paths. This feature simplifies earth
grounded controller applications that require opto-isolators to keep the 48-V return of the Ethernet power system
floating. For applications where opto-isolation is not required, the bidirectional property of the SDA line can be
restored by connecting SDA_I to SDA_O. The SCL line is a unidirectional input only line as the TPS23841 is
always accessed as a slave device and it never masters the bus.
TPS23841
SLUS745–NOVEMBER 2006
POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued)
Data transfers that require a data-flow reversal on the SDA line are 4-byte operations. This occurs during a
TPS23841 port read cycle where a slave address byte is sent, followed by a port/register address byte write. A
second slave address byte is sent followed by the data byte read using the port/register setup from the second
byte in the sequence.
The I
2
C interface and the port read write registers are held in active reset until all input voltages are within
specifications (V10, V6.3, V3.3 and V2.5) and the internal POR timer has timed out (see electrical
specifications).
The I
2
C read cycle consists of the following steps 1 through 14 and is shown in
Figure 16
:
1. Start Sequence (S)
2. Device address field
3. Write
4. Acknowledge
5. Register/Port address
6. Acknowledge
7. Stop
8. Start
9. Device address field
10. Read
11. Acknowledge
12. Data Transfer
13. Acknowledge
14. Stop
Data write transfers to the TPS23841 do not require a data-flow reversal and as such only a 3-byte operation is
required. The sequence in this case would be to send a slave device address byte, followed by a write of the
port/register address followed by a write of the data byte for the addressed port.
The I
2
C write cycle consists of the following steps 1 through 9 and is also shown in
Figure 16
:
1. Start sequence (S)
2. Device address field
3. Write
4. Acknowledge
5. Register/Port address
6. Acknowledge
7. Data for TPS23841
8. Acknowledge
9. Stop
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