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參數(shù)資料
| 型號(hào)： | TPS2345 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | CompactPCI Hot Swap Power Manager Industrial Temp IC that meets the PICMG Standard |
| 中文描述： | CompactPCI熱插拔電源管理集成電路工業(yè)溫度在PICMG符合標(biāo)準(zhǔn) |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大?。?/td> | 411K |
| 代理商： | TPS2345 |
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TPS2330, TPS2331
SINGLE HOT SWAP POWER CONTROLLER WITH
CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS277A – MARCH 2000– REVISED APRIL 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
DISCH –
DISCH should be connected to the source of the external N-channel MOSFET transistor connected
to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as
reference-voltage connection for internal gate-voltage-clamp circuitry.
ENABLE or ENABLE –
ENABLE for TPS2330 is active low. ENABLE for TPS2331 is active high. When the
controller is enabled, GATE voltage will power up to turn on the external MOSFETs. When the ENABLE pin is
pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50
μ
s, the gate of the
MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the
output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when
enabled and shuts down PREREG when disabled so that total supply current is much less than 5
μ
A.
FAULT
– FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long
enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low.
GATE
– GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled,
internal charge-pump circuitry pulls this pin up by sourcing approximately 15
μ
A. The turnon slew rates depend
upon the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced
by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect
the device from false overcurrent triggering during powerup. The charge-pump circuitry will generate
gate-to-source voltages of 9 V–12 V across the external MOSFET transistor.
IN
– IN should be connected to the power source driving the external N-channel MOSFET transistor connected
to GATE. The TPS2330/31 draws its operating current from IN, and will remain disabled until the IN power supply
has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.
ISENSE, ISET
– ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the
magnitude of the current that generates an overcurrent fault, through a external resistor connected to ISET. An
internal current source draws 50
μ
A from ISET. With a sense resistor from IN to ISENSE, which is also connected
to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent
condition is assumed to exist if ISENSE is pulled below ISET.
PWRGD
– PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain
output and is pulled low during an undervoltage condition. To minimize erronous PWRGD responses from
transients on the voltage rail, the voltage sense circuit incorporates a 20-
μ
s deglitch filter. When VSENSE is
lower than the reference voltage (about 1.23 V), PWRGD will be active low to indicate an undervoltage condition
on the power-rail voltage.
TIMER
– A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled
to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG
– The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current
from IN. A 0.1-
μ
F ceramic capacitor should be connected between VREG and ground. VREG can be connected
to IN or to a separated power supply through a low-resistance resistor. However, the voltage on VREG must
be less than 5.5 V.
VSENSE
– VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses
a voltage below approximately 1.23 V, PWRGD is pulled low.
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