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參數(shù)資料
| 型號(hào)： | TPA5050_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL |
| 中文描述： | 立體聲數(shù)字音頻口形同步延遲與I2C控制 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 782K |
| 代理商： | TPA5050_07 |
www.ti.com
SINGLE-BYTE WRITE
As shown is
Figure 6
, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I
2
C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I
2
C
device address and the read/write bit, the TPA5050 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the TPA5050 internal memory address being accessed. After
receiving the register byte, the TPA5050 again responds with an acknowledge bit. Next, the master device
transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the
TPA5050 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to
complete the single-byte data write transfer.
A6
A5
A4
A3
A2
A1
A0
R/W ACK
A7
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
Acknowledge
Acknowledge
I
2
C Device Address and
Read/Write Bit
Register
Data Byte
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TPA5050 as shown in
Figure 7
. After receiving each data byte, the
TPA5050 responds with an acknowledge bit.
Register
SINGLE-BYTE READ
As shown in
Figure 8
, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
TPA5050
SLOS492B–MAY 2006–REVISED MAY 2007
The TPA5050 supports sequential I
2
C addressing. For write transactions, if a register is issued followed by data
for that register and all the remaining registers that follow, a sequential I
2
C write transaction has taken place. For
I
2
C sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
Figure 6. Single-Byte Write Transfer
Figure 7. Multiple-Byte Write Transfer
After receiving the TPA5050 address and the read/write bit, the TPA5050 responds with an acknowledge bit.
The master then sends the internal memory address byte, after which the TPA5050 issues an acknowledge bit.
The master device transmits another start condition followed by the TPA5050 address and the read/write bit
again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA5050 transmits the data
byte from the memory address being read. After receiving the data byte, the master device transmits a
not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
8
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