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| 型號： | TPA3130D2DAPR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 7/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUD PWR 15W STER 32HTSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SpeakerGuard™ |
| 類型： | D 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 15W x 2 @ 8 歐姆 |
| 電源電壓： | 4.5 V ~ 26 V |
| 特點(diǎn)： | 差分輸入，靜音，短路和熱保護(hù)，關(guān)機(jī) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 32-HTSSOP |
| 封裝/外殼： | 32-TSSOP（0.240"，6.10mm 寬）裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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i
1
f
2 Z C
p
=
5
6
7
8
9
10
INNR
PLIMIT
GVDD
GAIN/SLV
GND
2
1
2
C5
1 F
2
1
51 k
R1
51 k
R2
SLOS708C – APRIL 2012 – REVISED NOVEMBER 2013
GAIN SETTING AND MASTER / SLAVE
The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or
Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four
stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets
the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up
and cannot be changed while device is powered. Table 1 shows the recommended resistor values and the state
and gain:
Table 1. GAIN and MASTER/SLAVE
MASTER / SLAVE
GAIN
R1 (to GND)(1)
R2 (to GVDD)(1)
INPUT IMPEDANCE
MODE
Master
20 dB
5.6 k
Ω
OPEN
60 k
Ω
Master
26 dB
20 k
Ω
100 k
Ω
30 k
Ω
Master
32 dB
39 k
Ω
100 k
Ω
15 k
Ω
Master
36 dB
47 k
Ω
75 k
Ω
9 k
Ω
Slave
20 dB
51 k
Ω
51 k
Ω
60 k
Ω
Slave
26 dB
75 k
Ω
47 k
Ω
30 k
Ω
Slave
32 dB
100 k
Ω
39 k
Ω
15 k
Ω
Slave
36 dB
100 k
Ω
16 k
Ω
9 k
Ω
(1)
Resistor tolerance should be 5% or better.
In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL
logic levels with compliance to GVDD.
INPUT IMPEDANCE
The TPA31xxD2 family input stage is a fully differential input stage and the input impedance changes with the
gain setting from 9 k
at 36 dB gain to 60 k at 20 dB gain. Table 1 lists the values from min to max gain. The
tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 k
. The inputs need to
be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-
ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter
with the following cut-off frequency:
(1)
If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz.
Table 2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10
times lower capacitors can used – for example, a 1 F can be used.
Table 2. Recommended Input AC-Coupling Capacitors
GAIN
INPUT IMPEDANCE
INPUT CAPACITANCE
HIGH-PASS FILTER
20 dB
60 k
Ω
1.5 F
1.8 Hz
26 dB
30 k
Ω
3.3 F
1.6 Hz
32 dB
15 k
Ω
5.6 F
2.3 Hz
36 dB
9 k
Ω
10 F
1.8 Hz
Copyright 2012–2013, Texas Instruments Incorporated
15
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