- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385009 > TP3406 (National Semiconductor Corporation) DASL Digital Adapter for Subscriber Loops PDF資料下載
參數(shù)資料
| 型號： | TP3406 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | DASL Digital Adapter for Subscriber Loops |
| 中文描述： | DASL適配器數(shù)字用戶環(huán)路 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 234K |
| 代理商： | TP3406 |
Connection Diagram
TP3406 Package Information
TL/H/11725–2
Order Number TP3406V
See NS Package Number V28A
Pin Descriptions
Name
Description
GND
Negative power supply pin, normally 0V. All
analog and digital signals are referred to this
pin.
V
CC
Positive power supply input, which must be
a
5V
g
5%.
The 2.048 MHz Master Clock input, which
requires a CMOS logic level clock input from
a stable source. Must be synchronous with
BCLK.
MCLK
MCLK/XTAL
This pin is the 2.048 MHz Master Clock in-
put, which requires either a crystal to be con-
nected between this pin and XTAL2 or a
CMOS logic level clock from a stable source,
which must be synchronous with BCLK.
XTAL2
This pin is the output side of the oscillator
amplifier.
MBS/FS
C
In Master Mode, this pin is the Master Burst
Sync input, which may be clocked at 4 kHz
to synchronize Transmit bursts from a num-
ber of devices at the Master end only. The 4
kHz should be nominally a square wave sig-
nal. If not used leave this pin open. In Slave
mode, this pin is a short Frame Sync output,
suitable for driving another DASL in Master
Mode to provide a regenerator (i.e. range-ex-
tender) capability.
BCLK
Bit Clock logic signal which determines the
data shift rate for B channel data on the digi-
tal interface side of the device. In Master
mode this pin is an input which may be any
multiple
of
8
kHz
2.048 MHz, but must be synchronous with
MCLK. In Slave mode this pin is an output at
2.048 MHz.
from
256
kHz
to
FS
a
In Master mode only, this pin is the Transmit
Frame Sync pulse input, requiring a positive
edge to indicate the start of the active chan-
nel time for transmit B channel data into B
x
;
FS
a
must be synchronous with BCLK and
MCLK. In Slave mode only, this pin is a digi-
Name
Description
tal output pulse which indicates the 8-bit pe-
riods of the B1 channel data transfer at both
B
x
and B
r
.
In Master mode only, this pin is the Receive
Frame Sync pulse input, requiring a positive
edge to indicate the start of the active chan-
nel time of the device for receive B channel
data out from B
r
; FS
b
must be synchronous
with BCLK and MCLK. In Slave mode only,
this pin is a digital output pulse which indi-
cates the 8-bit periods of the B2 channel
data transfer at both B
x
and B
r
.
Digital input for B1 and B2 channel data to
be transmitted to the line; must be synchro-
nous with BCLK.
FS
b
B
x
B
r
Digital output for B1 and B2 channel data
received from the line.
TS
r
/LSD
In Master mode only, this pin is an open-
drain output which is normally high imped-
ance but pulls low during both B channel ac-
tive receive time slots. In Slave mode only,
this pin is an output which is normally high
impedance and pulls low when a valid line
signal is received.
D
x
Digital input for D channel data to be trans-
mitted to the line; must be synchronous with
DCLK.
D
r
Digital output for D channel data received
from the line. D
r
is a TRI-STATE output.
In Master mode this pin is an input for the
16 kHz serial shift clock for D channel data
on D
x
and D
r
, which should be synchronous
with BCLK. It may also be re-configured via
the Control Register to act as an enable in-
put for clocking the D channel interface syn-
chronized to BCLK. In Slave mode this is a
16 kHz clock output for D channel data.
*
Crystal specifications: 2.048 MHz parallel resonant, R
S
s
100
X
with a
20 pF load. Crystal tolerance should be
g
75 ppm for aging and tempera-
ture.
DCLK/DEN
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3406V | DASL Digital Adapter for Subscriber Loops |
| TP3410 | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| TP3410J | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| TP3420AJ | ISDN S/T Interface Device |
| TP3420A | ISDN S/T Interface Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3406N/NOPB | 功能描述:IC ADAPTER DIG QDASL QUAD 20PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| TP3406V | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:DASL Digital Adapter for Subscriber Loops |
| TP3406V/NOPB | 功能描述:IC ADAPTER DIG QDASL QUAD 28PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| TP3407 E WAF | 制造商:Texas Instruments 功能描述: |
| TP3410 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。