參數(shù)資料
型號(hào): TP3406
廠商: National Semiconductor Corporation
英文描述: DASL Digital Adapter for Subscriber Loops
中文描述: DASL適配器數(shù)字用戶(hù)環(huán)路
文件頁(yè)數(shù): 13/16頁(yè)
文件大?。?/td> 234K
代理商: TP3406
Timing Characteristics
(Continued)
Unless otherwise noted: V
CC
e a
5V
g
5%, T
A
e
0
§
C to 70
§
C. Typical characteristics are specified at V
CC
e
5V, T
A
e
25
§
C.
All signals are referenced to GND.
Symbol
Parameter
Conditions
Min
Max
Units
D CHANNEL INTERFACE(Figure 11 &12)
t
SDDC
Set Up Time, D
X
Valid to DCLK Low
100
ns
t
HCD
Hold Time, DCLK Low
to D
X
Invalid
100
ns
t
DDCD
Delay Time, DCLK High to
D
r
Data Valid
Load
e
100 pF
a
2 LSTTL Inputs
220
ns
t
SDCB
Set-Up Time, DCLK
Transitions to BCLK High
Master Mode
Only
50
ns
t
HBDC
Hold Time, BCLK High
to DCLK Transitions
Master Mode
Only
50
ns
t
SDCF
Set-Up Time, DCLK
Transitions to FS
a
HIgh
Master Mode
Only
70
ns
t
DDED
Delay Time, DEN High
to D
r
Valid
Load
e
100 pF
a
2 LSTTL Inputs
200
ns
t
SDEB
Set-Up Time, DEN to
BCLK Low
100
ns
t
SDBC
Set-Up Time, D
x
to BCLK Low
50
ns
t
HBCD
Hold Time, BCLK
Low to D
x
Invalid
50
ns
t
DBCD
Delay Time, BCLK
High to D
r
Valid
Load
e
100 pF
a
2 LSSTL Inputs
190
ns
t
DCDZ
Delay Time, DEN
Low to D
r
High Impedance
140
ns
CONTROL INTERFACE(Figure 13)
t
CH
CCLK High Duration
250
ns
t
CL
CCLK Low Duration
250
ns
t
SIC
Setup Time, CI
Valid to CCLK High
100
ns
t
HCI
Hold Time, CCLK High
to CI Invalid
0
ns
t
SSC
Setup Time from CS
Low to CCLK High
200
ns
t
HCS
Hold Time from CCLK
Low to CS
10
ns
t
DCO
Delay Time from CCLK Low
to C0 Data Valid
Load
e
100 pF
a
2 LSTTL Inputs
150
ns
t
DSO
Delay Time from CS
Low to CO Valid
1st Bit Only
100
ns
t
DSZ
Delay Time from CS High
to CO High Impedance
100
ns
t
DCI
Delay Time from CCLK1
High to INT High Impedance
120
ns
13
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