參數(shù)資料
型號： TP3406
廠商： National Semiconductor Corporation
英文描述： DASL Digital Adapter for Subscriber Loops
中文描述： DASL適配器數(shù)字用戶環(huán)路
文件頁數(shù)： 14/16頁
文件大小： 234K
代理商： TP3406
Definitions and Timing Conventions
DEFINITIONS
V
IH
V
IH
is the d.c. input level above which
an input level is guaranteed to appear
as a logical one. This parameter is to
be measured by performing a function-
al test at reduced clock speeds and
nominal timing, (i.e. not minimum setup
and hold times or output strobes), with
the high level of all driving signals set
to V
IH
and maximum supply voltages
applied to the device.
V
IL
V
IL
is the d.c. input level below which
an input level is guaranteed to appear
as a logical zero to the device. This pa-
rameter is measured in the same man-
ner as V
IH
but with all driving signal low
levels set to V
IL
and minimum supply
voltages applied to the device.
V
OH
V
OH
is the minimum d.c. output level to
which an output placed in a logical one
state will converge when loaded at the
maximum specified load current.
V
OL
V
OL
is the maximum d.c. output level to
which an output placed in a logical zero
state will converge when loaded at the
maximum specified load current.
Threshold Region
The threshold region is the range of in-
put voltages between V
IL
and V
IH
.
Valid Signal
A signal is Valid if it is in one of the
valid logic states, (i.e. above V
IH
or be-
low V
IL
). In timing specifications, a sig-
nal is deemed valid at the instant it en-
ters a valid state.
Invalid Signal
A signal is Invalid if it is not in a valid
logic state, i.e. when it is in the thresh-
old region between V
IL
and V
IH
. In tim-
ing specifications, a signal is deemed
invalid at the instant it enters the
threshold region.
TIMING CONVENTIONS
For the purpose of this timing specification the following
conventions apply:
Input Signals
All input signals may be characterized
as: V
L
e
0.4V, V
IH
e
2.4V, t
R
k
10 ns,
t
F
k
10 ns.
Period
The period of clock signal is designat-
ed at t
Pxx
where xx represents the
mnemonic of the clock signal being
specified.
Rise Time
Rise times are designated at t
Ryy
,
where yy represents a mnemonic of
the signal whose rise time is being
specified. t
Ryy
is measured from V
IL
to
V
IH
.
Fall Time
Fall times are designated as t
Fyy
,
where yy represents a mnemonic of
the signal whose fall time is being
specified. t
Fyy
is measured from V
IH
to
V
IL
.
Pulse Width High
The high width is designated as t
WzzH
,
where zz represents the mnemonic of
the input or output signal whose pulse
width is being specified. High pulse
widths are measured from V
IH
to V
IH
.
Pulse Width Low
The low pulse width is designed as
t
WzzL
, where zz represents the mne-
monic of the input or output signal
whose pulse width is being specified.
Low pulse widths are measured from
V
IL
to V
IL
.
Setup Time
Setup times are designated as t
Swwxx
,
where ww represents the mnemonic of
the input signal whose setup time is be-
ing specified relative to a clock or
strobe input represented by mnemonic
xx. Setup times are measured from the
ww Valid to xx Invalid.
Hold Time
Hold times are designated as t
Hxxww
,
where ww represents the mnemonic of
the input signal whose hold time is be-
ing specified relative to a clock or
strobe input represented by mnemonic
xx. Hold times are measured from xx
Valid to ww invalid.
Delay Time
Delay times are designated as t
Dxxyy
[
l
H
l
L
]
, where xx represents the mne-
monic of the input reference signal and
yy represents the mnemonic of the out-
put signal whose timing is being speci-
fied relative to xx. The mnemonic may
optionally be terminated by an H or L to
specifiy the high going or low going
transition of the output signal. Maxi-
mum delay times are measured from xx
Valid to yy Valid. Minimum delay times
are measured from xx Valid to yy inval-
id. This parameter is tested under the
load conditions specified in the Condi-
tions column of the Timing Specifica-
tion section of this data sheet.
14
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