- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385009 > TP3404V (NATIONAL SEMICONDUCTOR CORP) Quad Digital Adapter for Subscriber Loops (QDASL) PDF資料下載
參數(shù)資料
| 型號(hào)： | TP3404V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Quad Digital Adapter for Subscriber Loops (QDASL) |
| 中文描述： | DATACOM, TIME SLOT ASSIGNER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 212K |
| 代理商： | TP3404V |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
Functional Description
(Continued)
LINE CONTROL REGISTERS CTRLN
Each of the 4 transceivers has a Line Control Register,
CTRL0–CTRL3, which provides for control of loop activa-
tion, Ioopbacks, Interrupt enabling and D channel interface
enabling. Table 3 lists the functions.
POWER ON INITIALIZATION
Following the initial application of power, the QDASL enters
the power-down (de-activated) state, in which all the internal
circuits are inactive and in a low power state except for a
Line-Signal Detect Circuit for each of the 4 lines, and the
necessary bias circuits. The 4 line outputs, Lo0–Lo3, are in
a high impedance state and all digital outputs are inactive.
All bits in the Line Control Registers power-up initially set to
‘‘0’’. While powered-down, each Line-Signal Detect Circuit
continually monitors its line, to detect if the far-end initiates
loop transmission.
POWER-UP/DOWN CONTROL
To power-up the device and initiate activation, bit C7 in any
of the 4 Line Control Registers must be set high, see Table
III. Setting C7 low de-activates the loop, or puts the channel
in power-down state. During power-down state, internal reg-
ister data is retained, and still can be accessed.
LOOPBACKS
Four different loopbacks can be set for each line. They are
enabled and disabled by setting the corresponding bits in
the Control Register, see Table III. In addition, a line must
be activated to see the effect of loopback commands.
1. 2B
a
D Line Loopback
When bit 5 is set to 1, this loop will transfer all three
channels, B1, B2 and D, that are received at the Li pin
back to the Lo pin. Data out on BO/DO is still the same
as received at the Li input.
2. B1 Line Loopback
When bit 4 is set high, the loop path is the same as (1)
but only data on the B1 channel is looped back to the
line. Transmit data in the B2 and D channels is from the
Bi/DI pins.
3. B2 Line Loopback
As (2) but for the B2 channel.
4. 2B
a
D Digital Loopback
This loop will transfer all data (2B
a
D) received at BI/DI
back to BO/DO. The data is also transmitted to the line.
TIME-SLOT ASSIGNMENT
The digital interface of the QDASL uses time-division multi-
plexing, with data framed in up to 64 possible 8-bit time-
slots per 125
m
s frame. Channels B1 and B2 for all 4 lines
are clocked in (towards the line) at the BI pin and clocked
out (from the line) at the BO pin. A separate port is provided
for the D channel data for all 4 lines, which is clocked in on
DI and out on DO. In addition to time-slot assignment, D
channel data may be assigned into 2-bit sub-slots within
each time slot, with up to 256 sub-slots per frame (with
BCLK
e
4.096 MHz). Each frame starts with the first posi-
tive edge of BCLK after the FS signal goes high, and count-
ing of timeslots starts from zero at the beginning of the
frame. Figure 4 shows the timing, with some example time-
slot assignments.
For each of the 4 QDASL lines there are 6 Time-Slot As-
signment control registers, one each for transmit and re-
ceive B1, B2 and D channels. Selection of time-slots for
transmit data into the BI or DI pin is made by writing the
timeslot number (in Hex notation) into the appropriate TSX
register. TSXB1 is the time-slot assignment for the transmit
B1, TSXB2 is the time-slot assignment register for the trans-
mit B2 channel and TSXD is the sub-slot assignment regis-
ter for the transmit D channel.
TABLE III. Byte 2 of Control Register (CTRLN)
Bit Number
Function
7
6
5
4
3
2
1
0
0
1
Deactivate Line
Activate Line
0
1
Disable Digital Loopback
Enable 2B
a
D Digital Loopback
0
1
Disable Line Loopback
Enable 2B
a
D Line Loopback
0
1
Disable B1 Line Loopback
Enable B1 Line Loopback
0
1
Disable B2 Line Loopback
Enable B2 Line Loopback
0
1
Disable Interrupt from this Line
Enable Interrupt from this Line
0
1
D Channel enabled from DO to Line
D Channel disabled from DO to Line
0
1
D Channel enabled from Line to DI
D Channel disabled from Line to DI
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3406 | DASL Digital Adapter for Subscriber Loops |
| TP3406V | DASL Digital Adapter for Subscriber Loops |
| TP3410 | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| TP3410J | TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver |
| TP3420AJ | ISDN S/T Interface Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3404V/63 | 功能描述:ISDN 接口 RoHS:否 制造商:Texas Instruments 封裝:Tube |
| TP3404V/63SN | 功能描述:ISDN 接口 RoHS:否 制造商:Texas Instruments 封裝:Tube |
| TP3404V/NOPB | 功能描述:ISDN 接口 RoHS:否 制造商:Texas Instruments 封裝:Tube |
| TP3406 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:DASL Digital Adapter for Subscriber Loops |
| TP3406N/NOPB | 功能描述:IC ADAPTER DIG QDASL QUAD 20PLCC RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。