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參數(shù)資料
| 型號(hào)： | TP3071AN |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | COMBO II Programmable PCM CODEC/Filter |
| 中文描述： | 組合二可編程PCM編解碼器/濾波器 |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 401K |
| 代理商： | TP3071AN |
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Programmable Functions
(Continued)
TABLE 5. Coding Law Conventions
μ255 law
True A-law with
even bit inversion
MSB
1 0 1 0 1 0 1 0
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 0 1 0 1 0 1 0
A-law without
even bit inversion
MSB
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
MSB
1 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
LSB
LSB
LSB
V
IN
= +Full Scale
V
IN
= 0V
V
IN
= Full Scale
Note 5:
The MSB is always the first PCM bit shifted in or out of COMBO II.
TABLE 6. Time-Slot and Port Assignment Instruction
Bit Number and Name
5
T
5
(Note 7)
X
Function
7
6
4
T
4
3
T
3
2
T
2
1
T
1
0
T
0
EN
PS
(Note 6)
0
0
X
X
X
X
X
Disable D
X
0 Output (Transmit Instruction)
Disable D
R
0 Input (Receive Instruction)
Disable D
X
1 Output (Transmit Instruction)
Disable D
R
1 Input (Receive Instruction)
Enable D
X
0 Output (Transmit Instruction)
Enable D
R
0 Input (Receive Instruction)
Enable D
X
1 Output (Transmit Instruction)
Enable D
R
1 Input (Receive Instruction)
0
1
X
X
X
X
X
X
1
0
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
Assign One Binary Coded Time-Slot from 0–63
1
1
Note 6:
The “PS” bit MUST always be set to 0 for the TP3071.
Note 7:
T5 is the MSB of the Time-slot assignment bit field. Time slot bits should be set to “000000” for both transmit and receive when operating in non-delayed
data timing mode.
5.0 TIME-SLOT ASSIGNMENT
COMBO II can operate in either fixed time-slot or time-slot
assignment mode for selecting the Transmit and Receive
PCM time-slots. Following power-on, the device is automati-
cally in Non-Delayed Timing mode, in which the time-slot al-
ways begins with the leading (rising) edge of frame sync in-
puts FS
and FS
. Time-Slot Assignment may only be used
with Delayed Data timing; see Figure 5 FS
and FS
may
have any phase relationship with each other in BCLK period
increments.
Alternatively, the internal time-slot assignment counters and
comparators can be used to access any time-slot in a frame,
using the frame sync inputs as marker pulses for the begin-
ning of transmit and receive time-slot 0. In this mode, a
frame may consist of up to 64 time-slots of 8 bits each. A
time-slot is assigned by a 2-byte instruction as shown in
Table 1 and Table 6 The last 6 bits of the second byte indi-
cate the selected time-slot from 0–63 using straight binary
notation. When writing a timeslot and port assignment regis-
ter, if the PCM interface is currently active, it is immediately
deactivated to prevent possible bus clashes. A new assign-
ment becomes active on the second frame following the end
of the Chip-Select for the second control byte. Rewriting of
register contents should not be performed during the talking
period of a connection to prevent waveform distortion
caused by loss of a sample which will occur with each regis-
ter write. The “EN” bit allows the PCM inputs, D
0/1, or out-
puts, D
X
0/1, as appropriate, to be enabled or disabled.
Time-Slot Assignment mode requires that the FS
and FS
R
pulses must conform to the delayed data timing format
shown in Figure 5
6.0 PORT SELECTION
On the TP3070 only, an additional capability is available; 2
Transmit serial PCM ports, D
X
0 and D
1, and 2 Receive se-
rial PCM ports, D
0 and D
1, are provided to enable
two-way space switching to be implemented. Port selections
for transmit and receive are made within the appropriate
time-slot assignment instruction using the “PS” bit in the sec-
ond byte. The PS bit selects either Port 0 or Port 1. Both
ports cannot be active at the same time.
On the TP3071, only ports D
0 and D
0 are available, there-
fore the “PS” bit MUST always be set to 0 for these devices.
Table 6 shows the format for the second byte of both trans-
mit and receive time-slot and port assignment instructions.
7.0 TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in Table 1
and Table 7 This corresponds to a range of 0 dBm0 levels at
VF
I between 1.619 Vrms and 0.087 Vrms (equivalent to
+6.4 dBm to 19.0 dBm in 600
).
To calculate the binary code for byte 2 of this instruction for
any desired input 0 dBm0 level in Vrms, take the nearest in-
teger to the decimal number given by:
200 x log
10
(V/0.08595)
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3071J | COMBO II Programmable PCM CODEC/Filter |
| TP3070V | COMBO II Programmable PCM CODEC/Filter |
| TP3071 | COMBO II Programmable PCM CODEC/Filter |
| TP3071N | COMBO II Programmable PCM CODEC/Filter |
| TP3070J | COMBO II Programmable PCM CODEC/Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3071AN-G | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3071J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3071N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3071NG | 制造商:National Semiconductor 功能描述:Audio Codec 1ADC / 1DAC 20-Pin PDIP Rail |
| TP3071N-G | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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