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參數(shù)資料
| 型號： | TP3071AN |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | COMBO II Programmable PCM CODEC/Filter |
| 中文描述： | 組合二可編程PCM編解碼器/濾波器 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 401K |
| 代理商： | TP3071AN |
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Programmable Functions
(Continued)
vice is powered-up or down by setting the “P” bit as indi-
cated. When the power-up or down control is entered as a
single byte instruction, bit one (1) must be reset to a 0.
When a power-up command is given, all de-activated circuits
are activated, but the TRI-STATE PCM output(s), D
0 (and
D
1), will remain in the high impedance state until the sec-
ond FS
X
pulse after power-up.
2.0 CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to the Control
Register is as shown in Table 1 The second byte has the fol-
lowing bit functions:
TABLE 2. Control Register Byte 2 Functions
Bit Number and Name
7
6
5
4
3
2
1
0
Function
F
1
F
0
MA
IA
DN
DL
AL
PP
0
0
MCLK = 512 kHz
0
1
MCLK = 1.536
1
0
MCLK = 2.048 MHz
1
1
MCLK = 4.096 MHz
0
X
Select μ-255 law (Note 4)
1
0
A-law, Including Even
Bit Inversion
1
1
A-law, No Even Bit Inversion
0
Delayed Data Timing
1
Non-Delayed Data
0
0
Normal Operation
1
X
Digital Loopback
0
1
Analog Loopback
0
Power Amp Enabled in PDN
1
Power Amp Disabled in
Note 4:
State at power-on initialization. (Bit 4 = 0)
2.1 Master Clock Frequency Selection
A Master clock must be provided to COMBO II for operation
of the filter and coding/decoding functions. The MCLK fre-
quency must be either 512 kHz, 1.536 MHz, 1.544 MHz,
2.048 MHz, or 4.096 MHz and must be synchronous with
BCLK. Bits F
and F
(see Table 2) must be set during initial-
ization to select the correct internal divider.
2.2 Coding Law Selection
Bits “MA” and “IA” in Table 2 permit the selection of μ255
coding or A-law coding, with or without even bit inversion.
2.3 Analog Loopback
Analog Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2 In the
analog loopback mode, the Transmit input VF
I is isolated
from the input pin and internally connected to the VF
O out-
put, forming a loop from the Receive PCM Register back to
the Transmit PCM Register. The VF
O pin remains active,
and the programmed settings of the Transmit and Receive
gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.
Hybrid balance must be disabled for meaningful analog loop-
back function.
2.4 Digital Loopback
Digital Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2 This
mode provides another stage of path verification by enabling
data written into the Receive PCM Register to be read back
from that register in any Transmit time-slot at D
0/1. In digital
loopback, the decoder will remain functional and output a
signal at VF
O. If this is undesirable, the receive output can
be turned off by programming the receive gain register to all
zeros.
3.0 INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface Latches as-
sume they are inputs, and therefore all IL pins are in a high
impedance state. Each IL pin may be individually pro-
grammed as a logic input or output by writing the appropriate
instruction to the LDR, see Table 1 and Table 3 For mini-
mum power dissipation, unconnected latch pins should be
programmed as outputs. For the TP3071, L5 should always
be programmed as an output.
Bits L
–L
must be set by writing the specified instruction to
the LDR with the L bits in the second byte set as follows:
TABLE 3. Byte 2 Functions of Latch Direction Register
Byte 2 Bit Number
5
4
L
2
L
3
7
L
0
6
L
1
3
L
4
2
L
5
1
X
0
X
L
n
Bit
0
1
IL Direction
Input
Output
X = don’t care
INTERFACE LATCH STATES
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc-
tion written to the Interface Latch Register (ILR) as shown in
Table 1 and Table 4 Latches configured as inputs will sense
the state applied by an external source, such as the
Off-Hook detect output of a SLIC. All bits of the ILR, i.e.
sensed inputs and the programmed state of outputs, can be
read back in the 2nd byte of a READ from the ILR.
It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed first,
followed immediately by the Latch Direction Register.
TABLE 4. Interface Latch Data Bit Order
Bit Number
4
D
3
7
6
5
3
2
1
X
0
X
D
0
D
1
D
2
D
4
D
5
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| TP3071J | COMBO II Programmable PCM CODEC/Filter |
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| TP3071 | COMBO II Programmable PCM CODEC/Filter |
| TP3071N | COMBO II Programmable PCM CODEC/Filter |
| TP3070J | COMBO II Programmable PCM CODEC/Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3071AN-G | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3071J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3071N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3071NG | 制造商:National Semiconductor 功能描述:Audio Codec 1ADC / 1DAC 20-Pin PDIP Rail |
| TP3071N-G | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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