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參數(shù)資料
| 型號： | TP3064J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| 中文描述： | MU-LAW, PCM CODEC, CDIP20 |
| 封裝： | 0.300 INCH, CERDIP-20 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 276K |
| 代理商： | TP3064J |
Electrical Characteristics
(Continued)
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
CC
e a
5.0V
g
5%, V
BB
e b
5.0V
g
5%; T
A
e
0
§
C to 70
§
C by correlation with 100% electrical testing at T
A
e
25
§
C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
CC
e
a
5.0V, V
BB
e b
5.0V, T
A
e
25
§
C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
I
I
XA
Input Leakage Current
b
2.5V
s
V
s
a
2.5V, VF
X
I
a
or VF
X
I
b
b
200
200
nA
R
I
XA
Input Resistance
b
2.5V
s
V
s
a
2.5V, VF
X
I
a
or VF
X
I
b
10
M
X
R
O
XA
Output Resistance
Closed Loop, Unity Gain
1
3
X
R
L
XA
Load Resistance
GS
X
10
k
X
C
L
XA
Load Capacitance
GS
X
50
pF
V
O
XA
Output Dynamic Range
GS
X
, R
L
t
10 k
X
VF
X
I
a
to GS
X
b
2.8
a
2.8
V
A
V
XA
Voltage Gain
5000
V/V
F
U
XA
Unity-Gain Bandwidth
1
2
MHz
V
OS
XA
Offset Voltage
b
20
20
mV
V
CM
XA
Common-Mode Voltage
CMRRXA
l
60 dB
b
2.5
2.5
V
CMRRXA
Common-Mode Rejection Ratio
DC Test
60
dB
PSRRXA
Power Supply Rejection Ratio
DC Test
60
dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
R
O
RF
Output Resistance
Pin VF
R
O
1
3
X
R
L
RF
Load Resistance
VF
R
O
e
g
2.5V
10
k
X
C
L
RF
Load Capacitance
Connect from VF
R
O to GNDA
25
pF
VOS
R
O
Output DC Offset Voltage
Measure from VF
R
O to GNDA
b
200
200
mV
ANALOG INTERFACE WITH POWER AMPLIFIERS (ALL DEVICES)
IPI
Input Leakage Current
b
1.0V
s
VPI
s
1.0V
b
100
100
nA
RIPI
Input Resistance
b
1.0V
s
VPI
s
1.0V
10
M
X
VIOS
Input Offset Voltage
b
25
25
mV
ROP
Output Resistance
Inverting Unity-Gain at
VPO
a
or VPO
b
1
X
F
C
Unity-Gain Bandwidth
Open Loop (VPO
b
)
400
kHz
C
L
P
GA
P
a
Load Capacitance
100
pF
Gain from VPO
b
to VPO
a
R
L
e
600
X
VPO
a
to VPO
b
Level at VPO
b
e
1.77 Vrms
b
1
V/V
PSRR
P
Power Supply Rejection of
V
CC
or V
BB
VPO
b
Connected to VPI
0 kHz
b
4 kHz
4 kHz
b
50 kHz
60
36
dB
dB
R
L
P
Load Resistance
Connect from VPO
a
to VPO
b
600
X
6
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TP3064N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3064V | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3064V/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3064V/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3064V-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
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