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參數(shù)資料
| 型號： | TP3064J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| 中文描述： | MU-LAW, PCM CODEC, CDIP20 |
| 封裝： | 0.300 INCH, CERDIP-20 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 276K |
| 代理商： | TP3064J |
Definitions and Timing Conventions
DEFINITIONS
V
IH
V
IH
is the d.c. input level above which
an input level is guaranteed to appear
as a logical one. This parameter is to
be measured by performing a
functional test at reduced clock
speeds and nominal timing, (i.e. not
minimum setup and hold times or
output strobes), with the high level of
all driving signals set to V
IH
and
maximum supply voltages applied to
the device
V
IL
is the d.c. input level below which
an input level is guaranteed to appear
as a logical zero to the device. This
parameter is measured in the same
manner as V
IH
but with all driving
signal low levels set to V
IL
and
minimum supply voltages applied to
the device.
V
OH
is the minimum d.c. output level
to which an output placed in a logical
one state will converge when loaded
at the maximum specified load current.
V
OL
is the maximum d.c. output level
to which an output placed in a logical
zero state will converge when loaded
at the maximum specified load current.
V
IL
V
OH
V
OL
Threshold Region The threshold region is the range of
input voltages between V
IL
and V
IH
.
Valid Signal
A signal is Valid if it is in one of the
valid logic states, (i.e. above V
IH
or
below V
IL
). In timing specifiations, a
signal is deemed valid at the instant it
enters a valid state.
Invalid Signal
A signal is Invalid if it is not in a valid
logic state, i.e. when it is in in the
threshold region between V
IL
and V
IH
.
In timing specifications, a signal is
deemed Invalid at the instant it enters
the threshold region.
TIMING CONVENTIONS
For the purposes of this timing specification, the following
conventions apply:
Input Signals
All input signals may be characterized
as: V
L
e
0.4V, V
H
e
2.4V, t
R
k
10 ns,
t
F
k
10 ns.
Period
The period of clock signal is
designated as t
Pxx
where xx
represents the mnemonic of the clock
signal being specified.
Rise Time
Rise times are designated as t
Ryy
,
where yy represents a mnemonic of
the signal whose rise time is being
specified. t
Ryy
is measured from V
IL
to
V
IH
.
Fall Time
Fall times are designated as t
Fyy
,
where yy represents a mnemonic of
the signal whose fall time is being
specified. t
Fyy
is measured from V
IH
to
V
IL
.
Pulse Width High
The high pulse width is designated as
t
WzzH
, where zz represents the
mnemonic of the input or output signal
whose pulse width is being specified.
High pulse widths are measured from
V
IH
to V
IH
.
Pulse Width Low
The low pulse width is designated as
t
WzzL
, where zz represents the
mnemonic of the input or output signal
whose pulse width is being specified.
Low pulse widths are measured from
V
IL
to V
IL
.
Setup Time
Setup times are designated as t
Swwxx
,
where ww represents the mnemonic of
the input signal whose setup time is
being specified relative to a clock or
strobe input represented by mnemonic
xx. Setup times are measured from the
ww Valid to xx Invalid.
Hold Time
Hold times are designated as t
Hxxww
,
where ww represents the mnemonic of
the input signal whose hold time is
being specified relative to a clock or
strobe input represented by mnemonic
xx. Hold times are measured from xx
Valid to ww Invalid.
Delay Time
Delay times are designated as t
Dxxyy
Hi to Low, where xx represents the
mnemonic of the input reference
signal and yy represents the
mnemonic of the output signal whose
timing is being specified relative to xx.
The mnemonic may optionally be
terminated by an H or L to specify the
high going or low going transition of
the output signal. Maximum delay
times are measured from xx Valid to yy
Valid. Minimum delay times are
measured from xx Valid to yy Invalid.
This parameter is tested under the
load conditions specified in the
Conditions column of the Timing
Specifications section of this data
sheet.
14
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PDF描述 |
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| TP3064N | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3064V | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
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| TP3067J | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3067N | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3064N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3064V | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3064V/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3064V/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3064V-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
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