參數(shù)資料
型號： TMX320DM647ZUT900
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 56/166頁
文件大小： 1341K
代理商： TMX320DM647ZUT900
www.ti.com
P
6
Peripheral Information and Electrical Specifications
6.1 Parameter Information
Transmission Line
4.0 pF
1.85 pF
Z0 = 50
(see Note)
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission
line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
42
3.5 nH
Device Pin
(see Note)
6.1.1
3.3-V Signal Transition Levels
Vref
V
ref
= V
IL
MAX (or V
OL
MAX)
V
ref
= V
IH
MIN (or V
OH
MIN)
6.1.2
3.3-V Signal Transition Rates
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of ac timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
All input and output timing parameters are referenced to V
ref
for both 0 and 1 logic levels. For 3.3-V I/O,
V
ref
= 1.5 V. For 1.8-V I/O, V
ref
= 0.9 V.
Figure 6-2. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to V
IL
MAX and V
IH
MIN for input clocks,
V
OL
MAX and V
OH
MIN for output clocks.
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
All timings are tested with an input edge rate of 4 volts per nanosecond (4 Vpns).
Peripheral Information and Electrical Specifications
56
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