參數(shù)資料
型號(hào)： TMX320DM647ZUT900
廠商： Texas Instruments, Inc.
英文描述： Digital Media Processor
中文描述： 數(shù)字媒體處理器
文件頁數(shù)： 102/166頁
文件大?。?/td> 1341K
代理商： TMX320DM647ZUT900
www.ti.com
P
AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/
ABA[1:0]
AED[63:0]
AAOE/ASOE
(A)
AR/W
AAWE/ASWE
(A)
AARDY
(B)
Byte Enables
Address
Read Data
Hold = 1
2
Strobe = 4
Setup = 1
2
2
4
10
10
1
1
1
3
DEASSERTED
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
6.10.3.2
Programmable Synchronous Interface Timing
Table 6-33. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see
Figure 6-18
)
-720
-900
NO.
UNIT
MIN
MAX
6
7
t
su(EDV-EKOH)
t
h(EKOH-EDV)
Setup time, read AEDx valid before AECLKOUT high
Hold time, read AEDx valid after AECLKOUT high
2
ns
ns
1.5
Table 6-34. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module
(1)
(see
Figure 6-18
–
Figure 6-20
)
-720
-900
NO.
PARAMETER
UNIT
MIN
1.3
MAX
4.9
4.9
1
2
3
4
5
8
9
10
11
12
t
d(EKOH-CEV)
t
d(EKOH-BEV)
t
d(EKOH-BEIV)
t
d(EKOH-EAV)
t
d(EKOH-EAIV)
t
d(EKOH-ADSV)
t
d(EKOH-OEV)
t
d(EKOH-EDV)
t
d(EKOH-EDIV)
t
d(EKOH-WEV)
Delay time, AECLKOUT high to ACEx valid
Delay time, AECLKOUT high to ABEx valid
Delay time, AECLKOUT high to ABEx invalid
Delay time, AECLKOUT high to AEAx valid
Delay time, AECLKOUT high to AEAx invalid
Delay time, AECLKOUT high to ASADS/ASRE valid
Delay time, AECLKOUT high to ASOE valid
Delay time, AECLKOUT high to AEDx valid
Delay time, AECLKOUT high to AEDx invalid
Delay time, AECLKOUT high to ASWE valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
4.9
1.3
1.3
1.3
4.9
4.9
4.9
1.3
1.3
4.9
Figure 6-18. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)
(A)
(1)
The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG):
Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency
Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has
been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CE_EXT = 1).
Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with
deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (R_ENABLE = 1).
Peripheral Information and Electrical Specifications
102
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