參數(shù)資料
型號: TMX320C6413ZTS500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 104/140頁
文件大小: 1958K
代理商: TMX320C6413ZTS500
Synchronous DRAM Timing
104
April 2004
Revised May 2005
SPRS247E
7.4
Synchronous DRAM Timing
Table 7
12. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 7
12)
NO.
400
500
UNIT
MIN
2.1
2.5
MAX
6
7
t
su(EDV-EKO1H)
t
h(EKO1H-EDV)
Setup time, read AEDx valid before AECLKOUTx high
Hold time, read AEDx valid after AECLKOUTx high
ns
ns
Table 7
13. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module (see Figure 7
12
Figure 7
19)
NO.
PARAMETER
400
500
UNIT
MIN
1.3
MAX
6.4
6.4
1
2
3
4
5
8
9
10
11
12
13
t
d(EKO1H-CEV)
t
d(EKO1H-BEV)
t
d(EKO1H-BEIV)
t
d(EKO1H-EAV)
t
d(EKO1H-EAIV)
t
d(EKO1H-CASV)
t
d(EKO1H-EDV)
t
d(EKO1H-EDIV)
t
d(EKO1H-WEV)
t
d(EKO1H-RAS)
t
d(EKO1H-ACKEV)
t
d(EKO1H-PDTV)
Delay time, AECLKOUTx high to ACEx valid
Delay time, AECLKOUTx high to ABEx valid
Delay time, AECLKOUTx high to ABEx invalid
Delay time, AECLKOUTx high to AEAx valid
Delay time, AECLKOUTx high to AEAx invalid
Delay time, AECLKOUTx high to ASDCAS valid
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
Delay time, AECLKOUTx high to ASDWE valid
Delay time, AECLKOUTx high to ASDRAS valid
Delay time, AECLKOUTx high to ASDCKE valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
6.4
1.3
1.3
6.4
6.4
1.3
1.3
1.3
1.3
6.4
6.4
6.4
14
Delay time, AECLKOUTx high to PDT valid
1.3
6.4
ns
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